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INTEGRATED CIRCUITS
DATA SHEET
P83Cx80; P87C380 Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
Product specification File under Integrated Circuits, IC20 1997 Dec 12
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
CONTENTS 1 1.1 1.2 2 3 4 5 5.1 5.2 6 6.1 7 7.1 7.2 7.3 8 8.1 8.2 8.3 8.4 9 10 10.1 10.2 11 11.1 11.2 11.3 11.4 12 13 13.1 13.2 13.3 14 14.1 14.2 14.3 15 15.1 FEATURES Differences from the 80C51 core Memory GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION General MEMORY ORGANIZATION Program memory Internal data memory Additional Special Function Registers INTERRUPTS Priority level structure How interrupts are handled Interrupt Enable Register (IE) Interrupt Priority Register (IP) WATCHDOG TIMER INPUT/OUTPUT (I/O) The alternative functions for Port 0, Port 1, Port 2 and Port 3 EMI (Electromagnetic Interference) reduction REDUCED POWER MODES Power Control Register Idle mode Power-down mode Status of external pins OSCILLATOR RESET External reset Power-on-reset T2 (Watchdog Timer) overflow ANALOG CONTROL (DC) 8-bit PWM outputs (PWM0 to PWM9) 14-bit PWM output (PWM10) A typical PWM output application ANALOG-TO-DIGITAL CONVERTER (ADC) Conversion algorithm 17.2 17.3 17.4 17.5 17.6 18 19 19.1 19.2 19.3 20 21 22 23 24 25 26 27 28 29 29.1 29.2 29.3 30 31 32 16 16.1 17 17.1
P83Cx80; P87C380
DIGITAL-TO-ANALOG CONVERTER (DAC) 8-bit Data Registers for the DAC outputs (DACn; n = 0 to 3) DISPLAY DATA CHANNEL (DDC) INTERFACE Special Function Registers related to the DDC interface Host type detection DDC1 protocol DDC2B protocol DDC2AB/DDC2B+ protocol RAM buffer for the system and DDC application I2C-BUS INTERFACE HARDWARE MODE DETECTION Special Function Register for mode detection and sync separation System description System operation POWER MANAGEMENT CONTROL MODES ONE TIME PROGRAMMABLE (OTP) VERSION LIMITING VALUES HANDLING DC CHARACTERISTICS DIGITAL-TO-ANALOG CONVERTER CHARACTERISTICS AC CHARACTERISTICS PACKAGE OUTLINE SOLDERING Introduction Soldering by dipping or by wave Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
1 FEATURES
P83Cx80; P87C380
* One 8-bit port only for I/O function * 20 derivative I/O ports with the specific port type configuration in each alternative function * Watchdog Timer with a programmable interval * On-chip Power-on-reset for low power detection * Special Idle and Power-down modes for reduced power operation * Optimized for Electromagnetic Compatibility (EMC) * Operating temperature: -25 to +85 C * Single power supply: 4.4 to 5.5 V. 1.1 Differences from the 80C51 core
* 80C51 type core * On-chip oscillator with a maximum frequency of 16 MHz (maximum 0.75 s instruction cycle) * A DDC interface: - That fully supports DDC1 with specific hardware - That is DDC2B, DDC2B+, DDC2AB (ACCESS.bus) compliant, based on a dedicated hardware I2C-bus interface. - Contains a specific AUX-RAM buffer with programmable size (128 or 256 bytes) that can be used for DDC operation and shared as system RAM * Automatic mode detection by hardware to capture the following information: - HSYNC frequency with 12-bit resolution - VSYNC frequency with 12-bit resolution - HSYNC and VSYNC polarity - HSYNC and VSYNC presence; needed for the VESA Device Power Management Signalling (DPMS) standard * On-chip sync processor comprising: - Composite sync separation - Free running mode - Clamping - Pattern generation * Two specific ports for the software I2C-bus interface * 4 analog voltage outputs derived from an 8-bit Digital-to-Analog Converter (DAC) * Ten 8-bit Pulse Width Modulation (PWM) outputs for digital control application * One 14-bit PWM output for digital control application * One 4-bit Analog-to-Digital Converter (ADC) with 2 input channels (for keyboard interface) * LED driver port (Port 0); eight port lines with 10 mA drive capability
* No external memory connection; signals EA, ALE and PSEN are not present. * Port 1, Port 2 and Port 3 (P3.0 to P3.3 only) mixed with other derivative functions. * Timer 0/Counter 0 and Timer 1/Counter 1: external input is removed. * External interrupt 0/INT0 replaced by Mode detection function. * Standard serial interface (UART) and its control register are removed. * Wake-up from Power-down mode is also possible by means of an interrupt. 1.2 Memory ROM/RAM sizes MEMORY DEVICE ROM P83C880 P83C180 P83C280 P83C380 P87C380 (OTP) 8 kbytes 16 kbytes 24 kbytes 32 kbytes 16 kbytes RAM 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes
Table 1
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
2 GENERAL DESCRIPTION
P83Cx80; P87C380
The P83Cx80; P87C380 denotes the following types: P83C880, P83C180, P83C280, P83C380 and P87C380, hereafter referred to as the P83C880, are monitor microcontrollers of the 80C51 family, with DDC (DDC1, DDC2B, DDC2B+ and DDC2AB) interface to the PC host. The internal hardware can separate composite sync signals and detect the various display modes. The digital/analog voltage outputs can be used to control the video and deflection functions the monitor. 3 ORDERING INFORMATION
This data sheet details the specific properties of the P83C880, P83C180, P83C280, P83C380 and P87C380. The shared characteristics of the 80C51 family of microcontrollers are described in "Data Handbook IC20", which should be read in conjunction with this data sheet.
PACKAGE(1) TYPE NUMBER NAME P83C880 P83C180 P83C280 P83C380 P87C380 (OTP) Note 1. For emulation the package CLCC84 is used. DESCRIPTION VERSION SOT270-1 SDIP42 plastic shrink dual in-line package; 42 leads (600 mil)
TEMPERATURE RANGE (C) -25 to +85
1997 Dec 12
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4
VSSA DAC0 to DAC3 ADC0(3) ADC1(3) SDA(1) SCL(1)
k, full pagewidth
VDDA
1997 Dec 12
VDD VSS 4
INT1
Philips Semiconductors
BLOCK DIAGRAM
XTAL1 PROGRAM MEMORY (4) 512 BYTES RAM 4 x 8-BIT DAC 4-BIT ADC SOFTWARE I2C-BUS SERIAL I/O DATA MEMORY
XTAL2
TWO 16-BIT TIMERS (T0, T1)
CPU
80C51 core excluding ROM/RAM
P83C880 P83C180 P83C280 P83C380 P87C380
8-bit internal bus
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
5
MODE DETECTION DDC INTERFACE 10 x 8-BIT PWM 14-BIT PWM WATCHDOG TIMER (T2) 10 internal reset CLAMP(3) VSYNCin HSYNCin CSYNCin(1) VSYNCout(1) PATOUT(3) HSYNCout(1) SDA1(1) SCL1(1) PWM0 to PWM7(2); PWM8 to PWM9(3) PWM10(1) RESET
MGG021
PARALLEL I/O PORTS & EXTERNAL BUS
INT0
4
P0
P1
P2
P3
(1) (2) (3) (4)
Alternative function of Port 1. Alternative function of Port 2. Alternative function of Port 3. ROM: 8 kbytes (P83C880); 16 kbytes (P83C180); 24 kbytes (P83C280); 32 kbytes (P83C380). EPROM: 16 kbytes only in the P87C180A.
P83Cx80; P87C380
Product specification
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
5 5.1 PINNING INFORMATION Pinning
P83Cx80; P87C380
handbook, halfpage
PWM7/P2.7 PWM6/P2.6 PWM5/P2.5 PWM4/P2.4 PWM3/P2.3 PWM2/P2.2 PWM1/P2.1 PWM0/P2.0 XTAL1
1 2 3 4 5 6 7 8 9
42 PWM8/CLAMP/P3.0 41 PWM9/PATOUT/P3.1 40 PWM10/P1.7 39 SCL/P1.0 38 SDA/P1.1 37 SCL1/P1.2 36 SDA1/P1.3 35 INT1/VPP 34 ADC1/P3.3
XTAL2 10 VDD 11 VSS 12 HSYNCin/PROG 13 HSYNCout/P1.5 14 CSYNCin/P1.6 15 VSYNCin/OE 16 VSYNCout/P1.4 17 P0.7 18 P0.6 19 P0.5 20 P0.4 21
P83C880 P83C180 P83C280 P83C380 P87C380
33 ADC0/P3.2 32 VDDA 31 VSSA 30 DAC3 29 DAC2 28 DAC1 27 DAC0 26 RESET 25 P0.0 24 P0.1 23 P0.2 22 P0.3
MGG020
Fig.2 Pinning configuration for SDIP42.
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
5.2 Pin description Pin description for SDIP42 (SOT270-1) PIN 41 42 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 26 31 32 33 34 35 36 37 38 39 40 Oscillator input pin for system clock. Oscillator output pin for system clock. Digital power supply (+5 V). Digital ground. DESCRIPTION
P83Cx80; P87C380
Table 2
SYMBOL PWM9/PATOUT/P3.1 PWM8/CLAMP/P3.0 PWM7/P2.7 PWM6/P2.6 PWM5/P2.5 PWM4/P2.4 PWM3/P2.3 PWM2/P2.2 PWM1/P2.1 PWM0/P2.0 XTAL1 XTAL2 VDD VSS HSYNCin/PROG HSYNCout/P1.5 CSYNCin/P1.6 VSYNCin/OE VSYNCout/P1.4 P0.7 to P0.0 RESET DAC0 to DAC3 VSSA VDDA ADC0/P3.2 ADC1/P3.3 INT1/VPP SDA1/P1.3 SCL1/P1.2 SDA/P1.1 SCL/P1.0 PWM10/P1.7
PWM9 to PWM0: 8-bit Pulse Width Modulation outputs 9 to 0. Pin 41 and 42 can also be used as the output pin of the test pattern display PATOUT and clamping out signal CLAMP respectively; PATOUT and CLAMP always have the higher priority. Alternative function general I/O ports; Port 3: P3.1 to P3.0 and Port 2: P2.7 to P2.0.
Horizontal sync input pin. During OTP programming it is used as the program pulse input (PROG). Horizontal sync output pin; alternative function: general I/O port P1.5. Composite sync input pin; alternative function: general I/O port P1.6. Vertical sync input pin. During OTP programming it is used as output strobe (OE). Vertical sync output pin; alternative function: general I/O port P1.4. Reset input; active HIGH initializes the device. Analog ground for DAC and ADC. Analog power supply (+5 V) for DAC and ADC. ADC analog input pins; alternative function: general I/O ports P3.2 and P3.3. External interrupt input pin. During OTP programming it is used as programming supply voltage pin; VPP = 12.75 V. I2C-bus serial data I/O port for the DDC2 interface; alternative function: general I/O port P1.3. I2C-bus serial clock I/O port for the DDC2 interface; alternative function: general I/O port P1.2. I2C-bus serial data I/O port; alternative function: general I/O port P1.1. I2C-bus serial clock I/O port; alternative function: general I/O port P1.0. 14-bit Pulse Width Modulation output 10; alternative function: general I/O port P1.7.
18 to 25 Port 0: general I/O ports; capability to drive LED. 27 to 30 8-bit DAC analog voltage output pins; output range: 0 to 5 V.
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
6 FUNCTIONAL DESCRIPTION
P83Cx80; P87C380
This chapter gives a brief overview of the device. Detailed functional descriptions are given in the following chapters: Chapter 7 "Memory organization" Chapter 8 "Interrupts" Chapter 9 "Watchdog Timer" Chapter 10 "Input/Output (I/O)" Chapter 11 "Reduced power modes" Chapter 12 "Oscillator" Chapter 13 "Reset" Chapter 14 "Analog control (DC)" Chapter 15 "Analog-to-digital converter (ADC)" Chapter 16 "Digital-to-analog converter (DAC)" Chapter 17 "Display Data Channel (DDC) interface" Chapter 18 "I2C-bus Interface" Chapter 19 "Hardware mode detection" Chapter 20 "Power management" Chapter 21 "Control modes". 6.1 General
In addition to the 80C51 standard functions, they provide a number of dedicated hardware functions for monitor application. Eight general I/O ports plus 20 functions combined I/O ports cater for application requirements adequately. Ten sets of 8-bit PWM deliver the digital waveform for analog control purposes. One 14-bit PWM can support F to V application. The keyboard interface is achieved via a 4-bit ADC. A Watchdog Timer with a maximum count period of 5 s prevents the processor running out of control due to malfunction. Four channels of linear DAC with 8-bit resolution support more accurate analog controls. One software I2C-bus interface is dedicated for the internal connection. A DDC interface will cover all DDC protocols, including DDC1, DDC2B, DDC2AB and DDC2B+. A hardware mode detector will facilitate mode detection even in power reduced modes, e.g. Idle mode. The versatile HSYNC and VSYNC outputs can be generated to serve the desired application. In the free running mode, two display patterns can highlight the status of the monitor. Accordingly, the following items will be supported by these microcontrollers: * Mode detection for: - Horizontal sync (HSYNC) frequencies from below 15 kHz up to 150 kHz - Vertical sync (VSYNC) frequencies from below 40 Hz up to 200 Hz * ACCESS.bus interfacing with external devices, e.g. PCs * DDC1, DDC2B, DDC2AB and DDC2B+ protocols as defined in the VESA DDC standard * Device Power Management Signalling (DPMS) as described in VESA DPMS proposal. Figure 1 shows the block diagram functions.
The P83C880, P83C180, P83C280, P83C380 and P87C380 8-bit microcontrollers are manufactured in an advanced CMOS process and are derivatives of the 80C51 microcontroller family. They have the same instruction set as the 80C51. They contain 512 bytes of data memory (RAM). ROM: 8 kbytes (P83C880); 16 kbytes (P83C180); 24 kbytes (P83C280); 32 kbytes (P83C380) and 16 kbytes of EPROM for the P87C180. The microcontrollers are intended for use in monitors ranging from 14" to 21" that can be controlled from the outside (e.g. by a PC) via the external DDC interface.
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
7 MEMORY ORGANIZATION
P83Cx80; P87C380
The Central Processing Unit (CPU) manipulates operands in two memory spaces. There are 512 bytes of internal data memory, consisting of 256 bytes standard RAM and 256 bytes RAM buffer which is accessible as the Auxiliary RAM (AUX-RAM) or addressed through DDCADR and RAMBUF. The memory map and address spaces are shown in Fig.3.
andbook, full pagewidth
overlapped space 255 INDIRECT ONLY INTERNAL 127 DIRECT AND INDIRECT 0 program memory area 0 internal data memory area 0
MGG028
32767(1) 24575(2) 16383(3) 8191(4)
255 SPECIAL FUNCTION REGISTERS AUX-RAM BUFFER
INDIRECT ONLY
(1) (2) (3) (4)
P83C380 and P87C380. P83C280. P380C180. P83C880.
Fig.3 Memory map and address spaces.
7.1
Program memory
The program memory consists of ROM: 8 kbytes (P83C880), 16 kbytes (P83C180), 24 kbytes (P83C280) and 32 kbytes (P83C380). The program memory implemented in the P87C380 is a 16 kbytes EPROM (OTP). 7.2 Internal data memory
The internal data memory is divided into three physically separated parts: 256 bytes of RAM, 256 bytes of AUX-RAM, and a 128 bytes Special Function Registers (SFRs) area. These can be addressed each in a different way as described in Sections 7.2.1 to 7.2.3 and Table 3. Table 3 Internal data memory map ADDRESS MODE MEMORY RAM LOCATION DIRECT 0 to 127(1) 128 to SFRs Notes 1. RAM locations 0 to 127 can be addressed directly and indirectly as in the 80C51. 2. RAM locations 128 to 255 can only be addressed indirectly. 255(2) X - - X INDIRECT X X X(3) - address pointer DDCADR and RAMBUF - address pointers are R0 and R1 of the selected register bank POINTERS
AUX-RAM 0 to 255 128 to 255
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
3. Indirect-addressable via MOVX-Datapointer or MOVX-Ri instructions. 7.2.1 RAM
BYTE ADDRESS (HEX)
P83Cx80; P87C380
BIT ADDRESS (HEX)
BYTE ADDRESS (DECIMAL)
Four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower RAM area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal 256 bytes RAM. The stack depth is only limited by the available internal RAM space of 256 bytes (see Fig.4). 7.2.2 SPECIAL FUNCTION REGISTERS (SFRS)
FFH
(MSB)
(LSB)
255
2FH 2EH 2DH 2CH 2BH 2AH 29H 28H 27H 26H 25H 24H 23H 22H 21H 20H 1FH 18H 17H
7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07
7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06
7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05
7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04
7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03
7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02
79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01
78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 24 23
The SFRs can only be addressed directly in the address range from 128 to 255 (see Fig.3). Figure 5 gives an overview of the Special Function Registers space. Sixteen address in the SFRs space are both byte and bit-addressable. The bit-addressable SFRs are those whose address ends in 0H and FH. The bit addresses in this area are 80H to FFH 7.2.3 AUX-RAM
AUX-RAM buffer 0 to 255 is indirectly addressable as external data memory locations 0 to 255 via MOVX-Datapointer instruction or via MOVX-Ri instruction. Since the external access function is not available, any access to AUX-RAM 0 to 255 will not affect the ports. The 256 bytes of AUX-RAM buffer used to support DDC interface is also available for system usage by indirect addressing through the address pointer DDCADR and data I/O buffer RAMBUF. The address pointer (DDCADR) is equipped with the post increment capability to facilitate the transfer of data in bulk (for details refer to Chapter 17). However, it is also possible to address the AUX-RAM buffer through MOVX command as usually used in the internal RAM extension of 80C51 derivatives.
BANK 3
BANK 2 10H 0FH BANK 1 08H 07H BANK 0 00H
MBH079
16 15 8 7 0
Fig.4 RAM bit addresses.
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
BYTE ADDRESS handbook, full pagewidth (HEX)
BIT ADDRESS (HEX)
BYTE ADDRESS (DECIMAL)
FFH
(MSB)
(LSB)
255
F8H F0H E8H E0H D8H D0H C8H C0H B8H B0H A8H A0H 98H 90H 88H 80H
FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87
FE F6 EE E6 DE D6 CE C6 BE B6 AE A6 9E 96 8E 86
FD F5 ED E5 DD D5 CD C5 BD B5 AD A5 9D 95 8D 85
FC F4 EC E4 DC D4 CC C4 BC B4 AC A4 9C 94 8C 84
FB F3 EB E3 DB D3 CB C3 BB B3 AB A3 9B 93 8B 83
FA F2 EA E2 DA D2 CA C2 BA B2 AA A2 9A 92 8A 82
F9 F1 E9 E1 D9 D1 C9 C1 B9 B1 A9 A1 99 91 89 81
F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80
MGG029
MDCST B PWME2 ACC S1CON PSW PWME1 DFCON IP0 P3 IEN0 P2 not used P1 TCON P0
Fig.5 Special Function Registers bit addresses.
1997 Dec 12
11
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
7.3 Additional Special Function Registers
P83Cx80; P87C380
The standard SFRs as used in 80C51 and the SFRs for some typical derivative functions like I2C-bus interface, Timer, etc. are described in the "Data Handbook IC20". The specific SFRs for the P83C880 are introduced in the relevant chapters. Some SFRs which are not mentioned or not dedicated to a certain function will be described in the following sections. All new additional SFRs used in the P83C880 are listed in Table 4. However, only some of them will be explained in detail in Sections 7.3.1 to 7.3.7. Table 4 Overview of additional SFRs DESCRIPTION RAM Buffer I/O Interface Register DDC Control Register DDC Address Pointer Data Shift Register for DDC1 Miscellaneous Control Register ADC Control Register PWM High-byte Data Latch PWM Low-byte Data Latch Control Register for DDC2 Status Register for DDC2 Data Shift Register for DDC2 Address Register for DDC2 PWM Output Control Register 1 PWM Output Control Register 2 Data Latches for 8-bit PWMs 8-bit Data Latches for 8-bit DACs Free run Control Register for HSYNCout Free run and Pulse width for HSYNCout Mode Detect Control and Status Register Free run Control Register for VSYNCout Free run and Pulse width for VSYNCout Pulse Generation Control Register Horizontal Period Counting High-byte Register Vertical Period Counting High-byte Register Vertical and Horizontal Period Counting Low-nibbles Register Watchdog Timer Data Register ADDRESS 9CH 9DH 9EH 9FH C0H C1H C6H C7H D8H D9H DAH DBH C8H E8H C9H to CFH, EDH to EFH E9H to ECH F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH RESET VALUE(1) READ/WRITE(2) XXXXXXXX X00X0000 00000000 00000000 10000000 XX000000 00000000 10000000 00000000 11111000 00000000 00000000 00000000 00000000 00000000 00000000 01100000 00011111 1X000000 01000000 XX000101 00000000 00000000 00000000 00000000 00000000 B UBBUBBBB B B B UUBBBBBRO B B B Ro B B B B B B B B BUBBRRRR B B B Ro Ro Ro B
REGISTER RAMBUF DDCCON DDCADR DDCDAT DFCON ADCDAT PWM10H PWM10L S1CON S1STA S1DAT S1ADR PWME1 PWME2 PWM0 to PWM9 DAC0 to DAC3 HFP HFPOPW MDCST VFP VFPOPW PULCNT HFHIGH VFHIGH VFLHFL T2 Notes
1. X = don't care; even if it's implemented. 2. B = both read/write and Ro = read only; accessible for the entire byte or an individual bit. U = not implemented.
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
7.3.1 RAM BUFFER I/O INTERFACE REGISTER (RAMBUF)
P83Cx80; P87C380
RAMBUF is used as an I/O interface to the RAM buffer. If it is associated with the address pointer DDCADR which is equipped with the capability of post increment, then it will be convenient to transfer the consecutive data stream. This feature is useful to support the DDC/EDID data transfer. Table 5 7 RAMBUF.7 Table 6 BIT 7 to 0 7.3.2 RAM Buffer I/O Interface Register (SFR address 9CH) 6 RAMBUF.6 5 RAMBUF.5 4 RAMBUF.4 3 RAMBUF.3 2 RAMBUF.2 1 RAMBUF.1 0 RAMBUF.0
Description of RAMBUF bits SYMBOL RAMBUF.7 to RAMBUF.0 DESCRIPTION 8-bit data which is read from or to be written into RAM buffer
MISCELLANEOUS CONTROL REGISTER (DFCON)
This register is bit-addressable. Table 7 7 EW2 Table 8 BIT 7 Miscellaneous Control Register (SFR address C0H) 6 SOGE 5 SYNCE 4 DDCE 3 S1E 2 ADCE 1 P14LVL 0 P8LVL
Description of DFCON bits SYMBOL EW2 DESCRIPTION Watchdog Timer enable flag. This flag is associated with the flags, EW1 (SFR PWM10H) and EW0 in (SFR PWM10L) to form the enable/disable control key for the Watchdog Timer (see Chapter 9). The Watchdog Timer is only disabled by EW2 to EW0 = 101, else it is kept enabled for the rest of the combinations. CSYNCin enable for pin CSYNCin/P1.6. If SOGE = 1, the pin function is CSYNCin. If SOGE = 0, the pin function is I/O port P1.6. Sync separated signals output enable for pins VSYNCout/P1.4 and HSYNCout/P1.5. If SYNCE = 1, the pins function as VSYNCout and HSYNCout respectively. If SYNCE = 0, the pins function as I/O ports P1.4 and P1.5 respectively. Enable for DDC interface pins SCL1/P1.2 and SDA1/P1.3. If DDCE = 1, the pins function as SCL1 and SDA1 respectively for the DDC interface. If DDCE = 0, the pins function as I/O ports P1.2 and P1.3 respectively. Enable for I2C-bus interface pins SCL/P1.0 and SDA/P1.1. If S1E = 1, the pins function as SCL and SDA respectively for the I2C-bus interface. If S1E = 0, the pins function as I/O ports P1.0 and P1.1 respectively.
6 5
SOGE SYNCE
4
DDCE
3
S1E
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
BIT 2 SYMBOL ADCE DESCRIPTION
P83Cx80; P87C380
ADC channel enable. This flag enables the ADC function and also switches the pins ADC0/P3.2 and ADC1/P3.3 to the ADC inputs function. If ADCE = 1, the ADC function is enabled and the pin functions are ADC0 and ADC1 respectively. If ADCE = 0, the ADC function is disabled and the pin functions are I/O ports P3.2 and P3.3 respectively. Polarity selection bit for the PWM10 output (14-bit PWM). If P14LVL = 1, PWM10 output is inverted. If P14LVL = 0, PWM10 output is not inverted. Polarity selection bit for the PWM0 to PMM9 outputs (8-bit PWM). If P8LVL = 1, PWM0 to PWM9 outputs are inverted. If P8LVL = 0, PWM0 to PWM9 outputs are not inverted.
1 0
P14LVL P8LVL
7.3.3 Table 9 7 -
ADC CONTROL REGISTER (ADCDAT) ADC Control Register (SFR address C1H) 6 - 5 DACHL 4 DAC3 3 DAC2 2 DAC1 1 DAC0 0 COMP
Table 10 Description of ADCDAT bits BIT 7 to 6 5 4 to 1 0 SYMBOL - DACHL DAC3 to DAC0 COMP Reserved. ADC input channels selection. If DACHL = 1, then input channel ADC1 is selected. If DACHL = 0, then input channel ADC0 is selected. Reference voltage level selection. The 4 bits select the analog output voltage (Vref) of the 8-bit DAC. For Vref values see Table 31. Comparison result; read only. If COMP = 1, then the ADC input voltage is higher than the reference voltage. If COMP = 0, then the ADC input voltage is lower than the reference voltage. DESCRIPTION
7.3.4
14-BIT PWM DATA LATCHES (PWM10H AND PWM10L)
Table 11 PWM High-byte Data Latch (PWM10H; SFR address C6H) 7 EW1 6 PWM10H.6 5 PWM10H.5 4 PWM10H.4 3 PWM10H.3 2 PWM10H.2 1 PWM10H.1 0 PWM10H.0
Table 12 Description of PWM10H bits BIT 7 SYMBOL EW1 DESCRIPTION Watchdog Timer enable flag. This flag is associated with the flag EW2 (SFR DFCON) and EW0 (SFR PWM10L) to form the enable/disable control key for the Watchdog Timer; see Tables 8 and 14. 7 upper data bits for the 14-bit PWM.
6 to 0
PWM10H.6 to PWM10H.0
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
Table 13 PWM Low-byte Data Latch (PWM10L; SFR address C7H) 7 EW0 6 PWM10L.6 5 PWM10L.5 4 PWM10L.4 3 PWM10L.3 2
P83Cx80; P87C380
1 PWM10L.1
0 PWM10L.0
PWM10L.2
Table 14 Description of PWM10L bits BIT 7 SYMBOL EW0 DESCRIPTION Watchdog Timer enable flag. This flag is associated with the flag EW2 (SFR DFCON) and EW1 (SFR PWM10H) to form the enable/disable control key for the Watchdog Timer; see Table 8 and 12. 7 lower data bits for the 14-bit PWM.
6 to 0 7.3.5
PWM10L.6 to PWM10L.0
PWM OUTPUT CONTROL REGISTER 1 (PWME1)
Table 15 PWM Output Control Register 1 (SFR address C8H) 7 PWME1.7 6 PWME1.6 5 PWME1.5 4 PWME1.4 3 PWME1.3 2 PWME1.2 1 PWME1.1 0 PWME1.0
Table 16 Description of PWME1 bits BIT 7 to 0 SYMBOL PWME1.7 to PWME1.0 DESCRIPTION PWM outputs enable; n = 7 to 0. If PWME1.n = 1, the corresponding PWM is enabled and pins PWMn/P2.n are switched to PWMn outputs. If PWME1.n = 0, the corresponding PWM is disabled and pins PWMn/P2.n are switched to I/O ports P2.n function.
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
7.3.6 PWM OUTPUT CONTROL REGISTER 2 (PWME2)
P83Cx80; P87C380
Table 17 PWM Output Control Register 2 (SFR address E8H) 7 PATENA 6 DACE3 5 DACE2 4 DACE1 3 DACE0 2 PWME2.2 1 PWME2.1 0 PWME2.0
Table 18 Description of PWME2 bits BIT 7 SYMBOL PATENA DESCRIPTION PATOUT (pattern output) enable. If PATENA = 1, the pin PWM9/PATOUT/P3.1 is switched to the PATOUT (display test pattern) output. If PATENA = 0, the PATOUT function is disabled. The PATOUT function always overrides other alternative functions such as PWM9 and P3.1. DAC outputs enable (n = 3 to 0). If DACEn = 1, the corresponding DACs: DAC3 to DAC0 are enabled. If DACEn = 0, the corresponding DACs: DAC3 to DAC0 are disabled. PWM outputs enable; n = 2 to 0. If PWME2.n = 1, the corresponding PWMs: PWM8, PWM9 and PWM10, are enabled by PWME2.2, PWME2.1 and PWME2.0 respectively and pins PWM8/CLAMP/P3.0, PWM9/PATOUT/P3.1 and PWM10/P1.7 are switched to PWM output. If PWME2.n = 0, the corresponding PWM is disabled. Pins PWM8/CLAMP/P3.0, PWM9/PATOUT/P3.1 and PWM10/P1.7 are switched to I/O port functions P3.0, P3.1 and P1.7 respectively.
6 to 3
DACE3 to DACE0
2 to 0
PWME2.2 to PWME2.0
7.3.7
DATA LATCHES FOR 8-BIT PWMS (PWM0 TO PWM9)
Table 19 Data Latches for 8-bit PWMs (n = 0 to 9; SFR address C9H to CFH and EDH to EFH) 7 PWMn.7 6 PWMn.6 5 PWMn.5 4 PWMn.4 3 PWMn.3 2 PWMn.2 1 PWMn.1 0 PWMn.0
Table 20 Description of PWM0 to PWM9 bits BIT 7 to 0 SYMBOL PWMn.7 to PWMn.0 DESCRIPTION 8-bit data for PWM channel n (n = 0 to 9)
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
8 INTERRUPTS
P83Cx80; P87C380
The P83C880 has 5 interrupt sources; these are shown in Fig.6. Interrupt INT1 is generated as in a normal 80C51 device. By means of IT1 in SFR TCON this interrupt can be selected to be: * Level sensitive, when IT1 = LOW; INT1 must be inactive before a return from interrupt instruction (RETI) is given, otherwise the same interrupt will occur again. * Edge sensitive, when IT1 = HIGH; the internal hardware will reset the latch when the LCALL instruction is executed for the vector address (see Table 21). Interrupt INT0 is generated by the mode change of mode detector. Interrupt INT0 is selected as edge or level sensitive by the state of the IT0 bit in the SFR TCON. However, it is recommended to always set IT0 to HIGH (edge sensitive) so that IE0 will be reset by the internal hardware when the LCALL instruction is executed for the vector address. Timer 0 and Timer 1 interrupts are generated by TF0 and TF1 which are set by an overflow of their respective Timer/Counter registers (except for Timer 0 in Mode 3; see "Data Handbook IC20; 80C51 Family; Chapter Timer/Counters"). When a timer interrupt is generated, the interrupt flag is cleared by the internal hardware when the LCALL instruction is executed for the vector address. The DDC interrupt is generated either by bit SI (SFR S1CON) for DDC2B/DDC2AB/DDC2B+ protocols or by bit DDC_int (SFR DDCCON) or by bit SWHINT (SFR DDCCON). These flags must be cleared by software. All bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled in software.
Each of these interrupts sources can be individually enabled or disabled by setting or clearing the bit in Special Function Register IE (see Table 23). IE also contains a global disable bit EA, which disables all interrupts at once. 8.1 Priority level structure
The priority level of each interrupt source can be individually programmed by setting or clearing a bit in Special Function Register IP (see Table 25). A low priority interrupt can itself be interrupted by a high priority interrupt, but not by another low priority interrupt. A high priority interrupt can not be interrupted by another interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If request of the same priority level is received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined as shown in Table 21. The IP register contains a number of reserved (in 80C51) bits: IP.7, IP.6 and IP.4. User software should not write logic 1s to these positions, since they may be used in other 80C51 family products. Table 21 Priority within levels SOURCE IE0 SI TF0 IE1 TF1 Note 1. The `Priority within level' structure is only used to resolve simultaneous requests of the same priority level. PRIORITY WITHIN LEVEL(1) 1 (highest) 2 3 4 5 (lowest)
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
handbook, full pagewidth
mode change interrupt
INT0 CHREQ
'0' IT0 '1' IE0 MUX IE0
SWITCH interrupt
SWH INT SI DDC INT
DDC1 interrupt
DDC2 (DDC2B/DDC2AB/DDC2B+) interrupt
S12 interrupt sources
Timer 0 overflow
TF0
TF0
external interrupt INT1
INT1
'0' IT1 '1' IE1 MUX IE1
Timer 1 overflow
TF1
TF1
MGG024
Fig.6 Interrupt sources.
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
8.2 How interrupts are handled
P83Cx80; P87C380
The interrupt flags are sampled at the S5P2 state of every machine cycle. The samples are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine, provided this hardware generated LCALL is not blocked by any of the following conditions: 1. An interrupt of equal priority or higher priority level is already in progress. 2. The current (polling) cycle is not the final cycle in the execution of the instruction in progress. 3. The instruction in progress is RETI or any write to the IE or IP registers. Any of these conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress will be completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any access to IE or IP, then at least one more instruction will be executed before the interrupt is vectored to.The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. Note that if an interrupt flag is active but not being responded to for one of the above mentioned conditions, and if the flag is still inactive when the blocking condition is removed, then the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is new. The polling cycle/LCALL sequence is illustrated in "Data Handbook IC20; 80C51 family hardware description; Figure: Interrupt Response Timing Diagram".
Note that if an interrupt of higher priority level becomes active prior to S5P2 of the machine cycle labelled C3 (see "Data Handbook IC20; 80C51 family hardware description; Figure: Interrupt Response Timing Diagram"), then in accordance with the above rules it will be vectored to during C5 and C6, without any instruction of the lower priority routine having been executed. Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine. The hardware generated LCALL pushes the contents of the Program Counter on to the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being vectored to as shown in Table 22. Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that the interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the Program Counter. Execution of the interrupted program continues from where it left off. Note that a simple RET instruction would also return execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress, making future interrupts impossible. Table 22 Vector addresses SOURCE IE0 SI TF0 IE1 TF1 VECTOR ADDRESS 0003H 002BH 000BH 0013H 001BH
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
8.3 Interrupt Enable Register (IE)
P83Cx80; P87C380
Table 23 Interrupt Enable Register (SFR address A8H) 7 EA 6 - 5 ES1 4 - 3 ET1 2 EX1 1 ET0 0 EX0
Table 24 Description of IE bits BIT 7 SYMBOL EA FUNCTION Disable all interrupts. If EA = 0, then no interrupt will be acknowledged. If EA = 1, then each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Reserved. Enable DDC interface interrupt. If ES1 = 1, then DDC interface interrupt is enabled. If ES1 = 0, then DDC interface interrupt is disabled. Reserved. Enable Timer 1 overflow interrupt. If ET1 = 1, then the Timer 1 interrupt is enabled. If ET1 = 0, then the Timer 1 interrupt is disabled. Enable external interrupt 1. If EX1 = 1 then the External 1 interrupt is enabled. If EX1 = 0 then the External 1 interrupt is disabled. Enable Timer 0 overflow interrupt. If ET0 = 1 then the Timer 0 interrupt is enabled. If ET0 = 0 then the Timer 0 interrupt is disabled. Enable mode change. If EX0 = 1 then the mode change interrupt is enabled. If EX0 = 0 then the mode change interrupt is disabled.
6 5 4 3 2 1 0
- ES1 - ET1 EX1 ET0 EX0
8.4
Interrupt Priority Register (IP)
Table 25 Interrupt Priority Register (address B8H) 7 - 6 - 5 PS1 4 - 3 PT1 2 PX1 1 PT0 0 PX0
Table 26 Description of IP bits BIT 7 to 6 5 4 3 2 1 0 - PS1 - PT1 PX1 PT0 PX0 SYMBOL Reserved. DDC interface Interrupt priority level. When PS1 = 1, DDC interface Interrupt is assigned a high priority level. Reserved. Timer 1 overflow interrupt priority level. When PT1 = 1, Timer 1 Overflow Interrupt is assigned a high priority level. External interrupt 1 priority level. When PX1 = 1, External Interrupt 1 priority is assigned a high priority level. Timer 0 overflow interrupt priority level. When PT0 = 1, Timer 0 Overflow Interrupt is assigned a high priority level. Mode change interrupt priority level. When PX0 = 1, Mode change Interrupt is assigned a high priority level. DESCRIPTION
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
9 WATCHDOG TIMER
P83Cx80; P87C380
In addition to the standard timers, a Watchdog Timer consisting of an 10-bit prescaler and an 8-bit timer is also incorporated. The timer is increased every 19.5 ms for an oscillator frequency of 16 MHz; this is derived from the oscillator frequency (fclk) by the formula: f clk f timer = ---------------------------304 x 1024 When a timer overflow occurs, the microcontroller is reset. To prevent a system reset, the timer must be reloaded before an overflows occurs, by the application software. If the processor suffers a hardware/software malfunction, the software will fail to reload the timer. This failure will produce a reset upon overflow thus preventing the processor running out of control. The Watchdog Timer can only be reloaded if the condition flag WLE (PCON.4) has been previously set by software. At the moment the counter is loaded the condition flag is automatically cleared. In the Idle mode the Watchdog Timer and reset circuitry remain active. The time interval between timer reloading and the occurrence of a reset, depends on the reloaded value.
The Watchdog Timer's time interval is: 1024 t = t 1 x ----------------------------( 256 - T2 ) Where T2 = decimal value of the T2 register contents and t1 = 15.2 s (fclk = 10 MHz); t1 = 12.7 s (fclk = 12 MHz) and t1 = 19 s (fclk = 16 MHz). For example, this may range from 19.5 ms to 5.0 s when using an oscillator frequency of 16 MHz. Table 27 lists the resolution and the maximum time interval of the Watchdog Timer using different system clocks. The Watchdog Timer is controlled by the Watchdog control bits: * EW2; DFCON.7 (SFR address C0H) * EW1; PWM10H.7 (SFR address C6H) * EW0; PWM10L.7 (SFR address C6H). Only when EW2 to EW0 = 101 the Watchdog Timer is disabled and allows the Power-down mode to be enabled. The rest of pattern combinations will keep the Watchdog Timer enabled and disable the Power-down mode. This security key with multiple flags split in two SFRs will prevent the Watchdog Timer from being terminated abnormally when the function of the Watchdog Timer is needed.
Table 27 Resolution and the maximum time interval of the WDT fclk (MHz) 10 12 16 304 PRESCALER FACTOR 152 RESOLUTION (ms) 15.56 12.97 19.46 MAXIMUM TIME INTERVAL (s) 4.0 3.3 5.0
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
10 INPUT/OUTPUT (I/O) The P83C880 has three 8-bit ports. Ports 0 to 2 are the same as in the 80C51, with the exception of the additional functions of Port 1 and Port 2. Port 3 only contains 4 bits. Port 3 also has alternative functions. All ports are bidirectional. Pins of which the alternative function is not used may be used as normal bidirectional I/Os. The use of Port 1, Port 2 and Port 3 pins as an alternative function is carried out automatically by the P83C880 provided the associated Special Function Register bit is set HIGH. The quasi-bidirectional type of port is applied for Port 1, Port 2 and Port 3. Port 0 is an open-drain I/O port with the capability to drive LED. However, for any port with an alternative function, while the alternative function is performed, the port type will be switched to the appropriate type against a specific function. The port types: quasi-bidirectional, pull-up and open-drain are shown in Figs 7, 8 and 9 respectively. 10.1 The alternative functions for Port 0, Port 1, Port 2 and Port 3
P83Cx80; P87C380
Port 2 Two alternative functions are provided: * High-order address in Programming/Verify mode for P87C380. * 8 channels of PWM outputs: PWM0/P2.0 to P2.7/PWM7. The port type in this situation is set as open-drain. Port 3 Two alternative functions are provided: * Two channels of PWM output: PWM8/CLAMP/P3.0 and PWM9/PATOUT/P3.1. The port type in this situation is set as open-drain. PATOUT and CLAMP functions always override PWM or port function even if they are enabled. For the PATOUT (pattern output) and CLAMP (clamping output) application, the port type is defined as push-pull. * Two pins for the software ADC input: ADC0/P3.2 and ADC1/P3.3. They are analog inputs. 10.2 EMI (Electromagnetic Interference) reduction
In order to reduce EMI (Electromagnetic Interference) the following design measures have been taken: * Slope control is implemented on all the I/O lines with alternative functions of the PWM, I2C-bus and DDC interface. For port pins P1.4 and P1.5, since the alternative functions VSYNCout and HSYNCout are incorporated, the driving capability is made as small as possible to reduce radiation and the slope control function is disabled to have a sharp output. Rise and fall time (10% to 90%) for slope control are: trf(min) < rise/fall time < trf(max). Refer to Chapter 27 for the detailed figures. * Placing the VDD and VSS pins next to each other * Double bonding of the VDD and VSS pins, i.e. 2 bondpads for each pin * Limiting the drive capability of clock drivers and prechargers * Applying slew rate controlled output drivers * Internal decoupling of the supply of the CPU core.
Port 0 Provides the low-order address in programming/verify mode for the P87C380. Port 1 Used for a number of special functions: * 2 I/O pins for I2C-bus interface: SCL/P1.0 and SDA/P1.1. The port type in this situation is set as open-drain. * 2 I/O pins for DDC interface: SCL1/P1.2 and SDA1/P1.3. The port type in this situation is set as open-drain. * 2 I/O pins for the outputs of sync separation: VSYNCout/P1.4 and HSYNCout/P1.5. The port type in this situation is set as push-pull. * One pin for the composite sync input of sync on green mode: CSYNCin/P1.6. There is no pull-up protection diode for this input pin. * One pin for the 14-bit PWM output: PWM10/P1.7. As PWM function, the port type is open-drain.
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
handbook, full pagewidth
strong pull-up 2 oscillator periods p1
VDD
p2 p3
I/O PIN Q from port latch n I1 input data read port pin INPUT BUFFER
MGG025
Fig.7 Standard output with quasi-bidirectional port.
handbook, full pagewidth
strong pull-up 2 oscillator periods '1' p1
VDD
p2 p3
I/O PIN Q from port latch n I1 input data read port pin INPUT BUFFER
MGG026
Fig.8 Standard output with the pull-up current source.
handbook, full pagewidth
strong pull-up 2 oscillator periods '0' p1
VDD
p2
I/O PIN Q from port latch n I1 input data read port pin INPUT BUFFER
MGG027
Fig.9 Standard output with the open-drain port.
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
11 REDUCED POWER MODES Two software selectable modes of reduced power consumption are implemented. These are the Idle mode and the Power-down mode. 11.1 Power Control Register (PCON)
P83Cx80; P87C380
The flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or during Idle mode. For example, the instruction that writes to PCON.0 can also set or clear both flag bits. When Idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. * The second way of terminating the idle mode is with an external hardware reset. Since the oscillator is still running, the hardware reset is required to be active for two machine cycles (24 oscillator periods) to complete the reset operation. * The third way of terminating the Idle mode is by an internal watchdog reset. In all cases the microcontroller restarts after 3 machine cycles. 11.3 Power-down mode
The Idle mode and Power-down mode are activated by software via the Power Control Register (SFR PCON). Its hardware address is 87H. PCON is not bit addressable. The reset value of PCON is 00H. 11.2 Idle mode
Idle mode operation permits the interrupts, I2C-bus interface, DDC interface, mode detection and timer blocks T0, T1 and T2 (Watchdog Timer) to function while the CPU is halted. The following functions are switched off when the microcontroller enters the Idle mode: * CPU (halted) * PWM0 to PWM10 (reset, output = HIGH) * 4-bit ADC (aborted if conversion is in progress) * DAC0 to DAC3 (output = indeterminate or frozen at the final value prior to the Idle instruction; decided by software). The following functions remain active during Idle mode; these functions may generate an interrupt or reset and thus terminate the Idle mode: * Timer 0, Timer 1 and Timer 2 (Watchdog Timer) * The DDC interface * External interrupt * Mode detection. The instruction that sets PCON.0 is the last instruction executed in the normal operating mode before Idle mode is activated. Once in the Idle mode, the CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, RAM and all other registers maintain their data during Idle mode. The status of external pins during Idle mode is shown in Table 28. There are three ways to terminate the Idle mode: * Activation of any enabled interrupt X0, T0, X1, T1 or S1 will cause PCON.0 to be cleared by hardware terminating Idle mode. The interrupt is serviced, and following return from interrupt instruction RETI, the next instruction to be executed will be the one which follows the instruction that wrote a logic 1 to PCON.0.
In Power-down mode the system clock is halted. The oscillator is frozen after setting the bit PD in the PCON register. The instruction that sets PCON.1 is the last executed prior to going into the Power-down mode. Once in Power-down mode, the oscillator is stopped.The content of the on-chip RAM and the Special Function Registers are preserved. Note that Power-down mode can not be entered when the Watchdog Timer has been enabled. The Power-down mode can be terminated by an external reset in the same way as in the 80C51 (but the SFRs are cleared due to RESET) or in addition by the external interrupt, INT1. A termination with INT1 does not affect the internal data memory and the Special Function Registers. This gives the possibility to exit from Power-down without changing the port output levels. To terminate the Power-down mode with an external interrupt, INT1 must be switched to be level-sensitive and must be enabled. The external interrupt input signal INT1 must be kept LOW till the oscillator has restarted and stabilized. The instruction following the one that put the device into the Power-down mode will be the first one which will be executed after the wake-up.
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
11.4 Status of external pins
P83Cx80; P87C380
* If the HSYNCout, VSYNCout, PATOUT or CLAMP output is selected (for selection see description in Tables 8 and 18) in Idle or Power-down mode, since sync separation is still alive in Idle mode, HSYNCout, VSYNCout, PATOUT or CLAMP output will be operating as normal. In Power-down mode: HSYNCout, VSYNCout, PATOUT or CLAMP output are pulled HIGH. * In Idle or Power-down mode, if bit DDCE (SFR DFCON) is set, the function of P1.2 and P1.3 will be switched to
the DDC interface pins SCL1 and SDA1 respectively. In Idle mode SCL1 and SDA1 can be active only if DDC1 or DDC2 is enabled; otherwise these pins are in the high-impedance (High-Z) state. * If bit PWME.n (SFR PWME1/PWME2) is set, the function of P1.7, P2.n, P3.0 and P3.1 will be switched to the PWM output function. However, in both Idle and Power-down modes, the output of those PWM pins are pulled HIGH.
Table 28 Status of external pins during Idle and Power-down modes PORT0 TO PORT 3 data data HSYNC; VSYNC; CLAMP; PATOUT operative HIGH SCL AND SDA High-Z High-Z SCL1 AND SDA1 operative High-Z PWM0 TO PWM10 HIGH HIGH DAC0 TO DAC3 unknown unknown
MODE
MEMORY
Idle Power-down
internal internal
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
12 OSCILLATOR The oscillator circuit of the P83C880 is a single-stage inverting amplifier in a Pierce oscillator configuration. The circuitry between XTAL1 and XTAL2 is basically an inverter biased to the transfer point. Either a crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuit. Both are operated in parallel resonance.
P83Cx80; P87C380
XTAL1 is the high gain amplifier input, and XTAL2 is the output (see Fig.10a). To drive the P83C880 externally, XTAL1 is driven from an external source and XTAL2 left open-circuit (see Fig.10b).
handbook, halfpage
handbook, halfpage
XTAL1
XTAL2
XTAL1
XTAL2 n.c.
MBE311
external clock (not TTL compatible)
MBE312
a.
Crystal oscillator; C = 20 pF.
b.
External clock drive.
handbook, halfpage
XTAL1
XTAL2
external clock (not TTL compatible)
MLC930 - 1
c.
External clock drive for P87C380.
Fig.10 Oscillator configurations.
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
13 RESET There are three ways to invoke a reset and initialize the P83C880: * Via the external RESET pin * Via the built-in Power-on-reset circuitry * Via the Watchdog Timer overflow. Table 29 Reset values of the Special Function Registers X = Undefined. The internal RAM is not affected by reset. ADDRESS 80H 81H 82H 83H 87H 88H 89H 8AH 8BH 8CH 8DH 90H 9CH 9DH 9EH 9FH A0H A8H B0H B8H C0H C1H C6H C7H C8H C9H CAH CBH CCH P0 SP DPL DPH PCON TCON TMOD TL0 TL1 TH0 TH1 P1 RAMBUF DDCCON DDCADR DDCDAT P2 IEN0 P3 IP0 DFCON ADCDAT PWM10H PWM10L PWME1 PWM0 PWM1 PWM2 PWM3 REGISTER CONTENT 1111 1111 0000 0111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 X00X 0000 0000 0000 0000 0000 1111 1111 0X0X 0000 XXXX 1111 XX0X 0000 1000 0000 XX00 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ADDRESS CDH CEH CFH D0H D8H D9H DAH DBH E0H E8H E9H EAH EBH ECH EDH EEH EFH F0H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH
P83Cx80; P87C380
Figure 11 illustrates the reset mechanism. Each reset source will activate an internal reset signal RSTOUT. The CPU responds by executing an internal reset and puts the internal registers in a defined state as shown in Table 29.
REGISTER PWM4 PWM5 PWM6 PSW S1CON S1STA S1DAT S1ADR ACC PWME2 DAC0 DAC1 DAC2 DAC3 PWM7 PWM8 PWM9 B HFP HFPOPW MDCST VFP VFPOPW PULCNT HFHIGH VFHIGH VFLHFL T2
CONTENT 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0110 0000 0000 0101 1X00 0000 0100 0000 XX00 0101 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
handbook, full pagewidth
VDD 10 F SCHMITT TRIGGER
RSTOUT RESET 8 k RRESET
RESET CIRCUITRY
overflow timer T2 on-chip circuit Power-on-reset
POC
MGG022
Fig.11 On-chip reset configuration.
13.1
External reset
Pin RESET is connected to a Schmitt trigger for noise reduction (see Fig.11). A reset is accomplished by holding the RESET pin HIGH for at least 16 machine cycles (192 system clocks) while the oscillator is running. An automatic reset can be obtained by switching on VDD, if the RESET pin is connected to VDD via a capacitor and a resistor as illustrated in Fig.11. The VDD rise time must not exceed 10 ms and the capacitor should be at least 10 F. The decrease of the RESET pin voltage depends on the capacitor and the external resistor RRESET. The voltage must remain above the lower threshold for at least the oscillator start-up time plus 2 machine cycles. 13.2 Power-on-reset
In the case of supply voltage fall, after the trip level Vt is reached, the power-on reset signal will follow the waveform of the supply voltage for time interval Tp. The time interval Tp guarantees that a complete power-on reset pulse can trigger the internal reset signal. However, to ensure that the oscillator is stable before the controller starts, the clock signals are gated away from the CPU for a further 2048 oscillator cycles. The values of Vt, Tp and a process tolerance of Vt can be found in Chapter 25; currently Vt = 3.9 V, Tp = 10 s and Vt = 0.3 V. 13.3 T2 (Watchdog Timer Data Register) overflow
An on-chip Power-on-reset circuit that detects the supply voltage rise or fall and accordingly generates a power-on reset pulse (see Fig.12). In the case of supply voltage rise, the power-on reset signal will follow the supply voltage rise; after reaching the trip level Vt the power-on reset signal will maintain the same behaviour, and returns to a LOW state after a time interval Tp.
The length of the output pulse from T2 is 3 machine cycles. A pulse of such short duration is necessary in order to recover from a processor or system fault as fast as possible.
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
Vt
handbook, full pagewidth
supply voltage
Vt
Power-on-reset
oscillator
CPU running 2048 clocks start-up Tp Tp 2048 clocks
MGG023
Fig.12 Power-on reset switching level.
1997 Dec 12
29
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
14 ANALOG CONTROL (DC) The P83C880 has eleven Pulse Width Modulated (PWM) outputs for analog control purposes e.g. brightness, contrast, E-W, R (or G or B) gain control etc. Each PWM output generates a pulse pattern with a programmable duty cycle. The eleven PWM outputs comprise: * 10 PWM outputs with 8-bit resolution (PWM0 to PWM9); described in Section 14.1. * 1 PWM output with 14-bit resolution (PWM10); described in Section 14.2. A typical PWM output application is described in Section 14.3. 14.1 8-bit PWM outputs (PWM0 to PWM9)
P83Cx80; P87C380
The polarity of the PWM outputs is programmable and is selected by the P8LVL bit in SFR DFCON (address C0H); see Table 4. The duty cycle of outputs PWM0 to PWM9 is dependent on the programmable contents of the data latches: SFRs PWM0 to PWM9. As the clock frequency of each PWM circuit is 14fclk, the pulse width of the pulse generated can 4 x ( PWMn ) be calculated as: Pulse width = --------------------------------f clk Where (PWMn) is the decimal value held in the relevant data latch. The maximum repetition frequency of the 8-bit PWM f clk outputs is: f PWM = -----------1024 The block diagram for the 8-bit PWM outputs is shown in Fig.13.
PWM outputs PWM0 to PWM9 share the same pins as port lines P2.0 to P2.7, P3.0 and P3.1 respectively. Selection of the pin function as either a PWM output or a port line is achieved using the appropriate PWMnE bit in SFRs, PWME1 (address C8H) and PWME2 (address E8H); see Table 4.
handbook, full pagewidth
internal data bus
fclk 4
8-BIT PWM DATA LATCH
P8LVL
P2.x/P3.x data I/O
PWMnE
8-BIT DAC PWM CONTROLLER
Q Q P2.x/P3.x/PWMn
MGG042
Fig.13 Block diagram for 8-bit PWMs.
1997 Dec 12
30
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
handbook, ffull pagewidth clk
4 256 1 2 3 m m+1 m+2 256 1
00
01
m
255
decimal value PWM data latch
MGG043
Fig.14 PWM0 to PWM9 output patterns.
14.2
14-bit PWM output (PWM10)
PWM10 shares the same pin as port line P1.7. Selection of the pin function as either a PWM output or as a port line is achieved using the PWME2.0 bit in SFR PWME2 (address E8H); see Table 4. The block diagram for the 14-bit PWM output is shown in Fig.15 and comprises: * Two 7-bit latches; SFRs PWM10H and PWM10L * 14-bit data latch (PWMREG) * 14-bit counter * Coarse pulse controller * Fine pulse controller * Mixer. Data is loaded into the 14-bit data latch (PWMREG) from the two 7-bit data latches (PWM10H and PWM10L) when PWM10H is written to. The upper seven bits of PWMREG are used by the coarse pulse controller and determine the coarse pulse width; the lower seven bits are used by the fine pulse controller and determine in which subperiods fine pulses will be added.
The outputs OUT1 and OUT2 of the coarse and fine pulse controllers are then `ORed' in the mixer to give the PWM10 output. The polarity of the PWM10 output is programmable and is selected by the P14LVL bit in SFR DFCON (address C0H); see Section 7.3.2. As the 14-bit counter is clocked by 14fclk, the repetition times of the coarse and fine pulse controllers may be calculated as shown below. 4 Coarse controller repetition time: t sub = 128 x -----f clk 4 Fine controller repetition time: t r = 128 x 128 x -----f clk Figure 16 shows typical PWM10 outputs, with coarse adjustment only, for different values held in PWM10H, when P14LVL = 1. Figure 17 shows typical PWM10 outputs when P14LVL = 1, with coarse and fine adjustment, after the coarse and fine pulse controller outputs have been `ORed' by the mixer. When P14LVL = 1, the PWM10 output is inverted.
1997 Dec 12
31
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
handbook, full pagewidth
internal data bus
`MOVE instruction'
PWM10H
PWM10L
`MOV instruction'
7
7
DATA LOAD TIMING PULSE
LOAD
PWMREG
7
7
COARSE 7-BIT PWM OUT1
FINE PULSE GENERATOR OUT2
MIXER polarity control bit Q Q
PWM10 output P14LVL Q14 to 8 14-BIT COUNTER Q7 to 1 fclk 4
MGG044
Fig.15 14-bit PWM block diagram.
1997 Dec 12
32
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
14.2.1 COARSE ADJUSTMENT
P83Cx80; P87C380
An active HIGH pulse is generated in every subperiod; the pulse width being determined by the contents of PWM10H. The coarse output (OUT1) is HIGH at the start of each subperiod and will remain HIGH until the time [4/fclk x (128 - PWM10H)] has elapsed. The output will then go LOW and remain LOW until the start of the next subperiod. The coarse pulse width may be calculated as: 4 Pulse duration = ( PWM10H ) x -----f clk 14.2.2 FINE ADJUSTMENT
For example, if PWM10L = 000 0101 then this is a combination of: * PWM10L = 000 0001: subperiod 64 * PWM10L = 000 0100: subperiods 16, 48, 80 and 112. Pulses will be added in subperiods 16, 48, 64, 80 and 112. This example is illustrated in Fig.18. When PWM10L holds 000 0000 fine adjustment is inhibited and the PWM10 output is determined only by the contents of PWM10H. Table 30 Additional pulse distribution PWM10L 000 0001 000 0010 000 0100 000 1000 001 0000 010 0000 100 0000 ADDITIONAL PULSE IN SUBPERIOD 64 32 and 96 16, 48, 80 and 112 8, 24, 40, 56, 72, 88, 104 and 120 4, 12, 20, 28, 36, 44, 52...116 and 124 2, 6, 10, 14, 18, 22, 26, 30...122 and 126 1, 3, 5, 7, 9, 11, 13, 15, 17...125 and 127
Fine adjustment is achieved by generating an additional pulse in specific subperiods. The pulse is added at the start of the selected subperiod and has a pulse width of 4/fclk. The contents of PWM10L determine in which subperiods a fine pulse will be added. It is the logic 0 state of the value held in PWM10L that actually selects the subperiods. When more than one bit is a logic 1 then the subperiods selected will be a combination of those subperiods specified in Table 30.
f full handbook,clk pagewidth 4 127 00 0 1 2 128 - (m + 1) 128 - (m - 1) 128 - m 127 0 1
01
m
127
MGG045
decimal value PWM7H data latch
Fig.16 PWM10 output patterns: Coarse adjustment only.
1997 Dec 12
33
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync
P83Cx80; P87C380
fclk handbook, full pagewidth 4 127 0 1 2 128 - (m + 1) 128 - (m - 1) 128 - m 127 0 1
00
01
m
127 decimal value PWM10H data latch
MGG046
Fig.17 PWM10 output patterns: Coarse and fine adjustment (PWM10L = 000 0000B).
handbook, full pagewidth
tr
tsub0
tsub16
tsub32
tsub48
tsub64
tsub80
tsub96
tsub112
tsub127
000 0001
000 0100
000 0101 PWM10L
MGG047
Fig.18 Fine adjustment output (OUT2).
1997 Dec 12
34
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
14.3 A typical PWM output application
P83Cx80; P87C380
A typical PWM application is shown in Fig.19. The buffer is optionally used to reduce the influence from supply/ground bouncing to another circuit. R1 and C1 form the integration network, the time constant of which should be equal to or greater than 5 times the repetition period of the PWM output pattern. In order to smooth a changing PWM output a high value of C1 should be chosen. The value of C1 will normally be in the range 1 to 10 F. The potential divider chain formed by R2 and R3 is used only when the output voltage is to be offset. The output voltages for this application are calculated using Equations (1) and (2). R3 x V DD (1) V max = -----------------------------------R1 x R2 R3 + --------------------R1 + R2 R1 x R3 --------------------- x V DD R1 + R3 = --------------------------------------R1 x R3 R2 + --------------------R1 + R3
andbook, halfpage
supply voltage R2 R1 PWMn analog output C1 VSS R3
DEVICE TYPE NR. (1)
MGG048
V min
(2)
The loop from the PWM pin through R1 and C1 to VSS will radiate high frequency energy pulses. In order to limit the effect of this unwanted radiation source, the loop should be kept short and a high value of R1 selected. The value of R1 will normally be in the range 3.3 to 100 k. It is good practice to avoid sharing VSS (pin 12) with the return leads of other sensitive signals.
(1) P83Cx80; P87C380
Fig.19 Typical PWM output circuit.
1997 Dec 12
35
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
15 ANALOG-TO-DIGITAL CONVERTER (ADC) The ADC inputs ADC0 and ADC1 share the same pins as port lines P3.2 and P3.3 respectively. Selection of the pin function as either an ADC input or as a port line is achieved using bit ADCE in SFR DFCON (address C0H). When ADCE = 1, the ADC function is enabled; see Section 7.3.2, Table 8. The two channel ADC comprises a 4-bit Digital-to-Analog Converter (DAC); a comparator; an analog channel selector and control circuitry. As the digital input to the 4-bit DAC is loaded by software (a subroutine in the program), it is known as a software ADC. The block diagram is shown in Fig.20. The 4-bit DAC analog output voltage (Vref) is determined by the decimal value of the data held in bits DAC0 to DAC3 (DAC value) of SFR ADCDAT (address C1H). Vref is V DD calculated as: V ref = --------- x ( DAC value + 1 ) 16 Table 31 lists the Vref values as function of DAC3 to DAC0. When the analog input voltage is higher than Vref, the COMP bit in SFR ADCDAT (address C1H) will be HIGH. The channel selector, consisting of two analog switches, is controlled by bit DACHL in SFR ADCDAT; see Table 32. Table 31 Selection of Vref DAC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DAC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DAC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DAC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vref (V)
1 2 3 4 5 6 7 8 9 16 16 16 16 16 16 16 16
P83Cx80; P87C380
Table 32 Selection of ADC channel DACHL 0 1 15.1 Conversion algorithm CHANNEL SELECTED ADC0 ADC1
There are many algorithms available to achieve the ADC conversion. The algorithm described below and shown in Fig.21 uses an iteration process. 1. Select ADCn channel for conversion. Channel selection is achieved using bit DACHL, SFR ADCDAT (address C1H). 2. Set the digital input to the DAC to 1000. The digital input to the DAC is selected using bits DAC3 to DAC0 (SFR ADCDAT). 3. Determine the result of the compare operation. This is achieved by reading the COMP bit in SFR ADCDAT using the instruction `MOV A, ADCDAT'. If COMP = 1; the analog input voltage is higher than the reference voltage (Vref). If COMP = 0; the analog input voltage is lower than the reference voltage (Vref). 4. If COMP = 1; then the analog input voltage is higher than the reference voltage (Vref) and therefore the digital input to the DAC needs to be increased. Set the input to the DAC to 1100. 5. If COMP = 0; then the analog input voltage is lower than the reference voltage (Vref) and therefore the digital input to the DAC needs to be decreased. Set the input to the DAC to 0100. 6. Determine the result of the compare operation by reading the COMP bit in SFR ADCDAT. 7. For the DAC = 1100 case. If COMP = 1; then the analog input voltage is still greater than Vref and therefore the digital input to the DAC needs to be increased again. Set the input to the DAC to 1110. If COMP = 0; then the analog input voltage is now less than Vref and therefore the digital input to the DAC needs to be decreased. Set the input to the DAC to 1010.
x VDD x VDD x VDD x VDD x VDD x VDD x VDD x VDD
16 x VDD 10 x V 16 DD 11 x V 16 DD 12 x V 16 DD 13 x V 16 DD 14 x V 16 DD 15 x V 16 DD
VDD
1997 Dec 12
36
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
8. For the DAC = 0100 case. If COMP = 1; then the analog input voltage is now greater than Vref and therefore the digital input to the DAC needs to be increased. Set the input to the DAC to 0110. If COMP = 0; then the analog input voltage is still lower than Vref and therefore the digital input to the DAC needs to be decreased again. Set the input to the DAC to 0010. 9. The operations detailed in 5, 6 and 7 above are repeated and each time the digital input to the DAC is changed accordingly; as dictated by the state of the COMP bit.
P83Cx80; P87C380
The complete process is shown in Fig.21. Each time the DAC input is changed the number of values which the analog input can take is reduced by half. In this manner the actual analog value is honed into. The value of the analog input (VA) is determined by the formulae: V DD V A = --------- x ( DAC value + 1 ) 16 As the conversion time of each compare operation is greater than 6 s but less than 9 s; a NOP instruction is recommended to be used in between the instructions that select Vref; the ADC channel and read the COMP bit.
handbook, full pagewidth
internal bus PORT INTERFACE EN0 EN1
P3.3/ADC1 ADC CHANNEL SELECTOR P3.2/ADC0 + Vref COMPARATOR - EN COMP bit MOV A, ADCDAT instruction to read COMP bit
channel selection
DACHL
ENABLE SELECTOR 4-BIT DAC
ADCE ADC enable selection DAC3 DAC2 DAC1 DAC0
MGG049
DAC value selection
Fig.20 Block diagram of the ADC.
1997 Dec 12
37
P83Cx80; P87C380
Product specification
Fig.21 Example of converting algorithm for software ADC.
handbook, full pagewidth
1997 Dec 12
Value = 0111 T COMP = 1 -0100 F Value = 0011 F -0010 COMP = 1 +0010 -0010 T F Value = 1001 Value =0101 Value = 0001 +0001 COMP = 1 COMP = 1 T -0001 +0001 -0001 F T F +0001 T COMP = 1 F -0001
Philips Semiconductors
+0100
Value = 1011
+0010
T
COMP = 1
Value = 1101
+0001
T
COMP = 1
F
-0001
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
38
Value = 1010 Value = 1000 Value = 0110 Value = 0100 COMP = 1 T 1011 1010 1001 1000 0111 0110 F T F T F T 0101 COMP = 1 COMP = 1 COMP = 1 F 0100 T
Value = 1110
Value = 1100
Value = 0010
Value = 0000
COMP = 1
COMP = 1
COMP = 1 F 0011 0010 T 0001
COMP = 1 F 0000
MBK518
T
F
T
F
1111
1110
1101
1100
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
16 DIGITAL-TO-ANALOG CONVERTER (DAC) Four channels of linear voltage outputs mainly for the horizontal and vertical position control are provided from four sets of the Digital-to-Analog Converter (DAC). The DACs are well tuned to meet the following specific system requirements of the monitor. * For a 21'' monitor, the shift per step by changing the data of the DAC is expected to be 0.5 mm. Accordingly, the DAC with 8-bit resolution is required. * To avoid visible position shift due to environmental temperature change, the drift of output level of the DAC is less than 1.5 mV/C. * To eliminate the visible jitter, the maximum tolerable ripple for the output voltage of the DAC is less than 2 mV. Each DAC comprises an 8-bit data latch, a voltage scaling mechanism and an output driver. A precise current reference is provided internally to serve 4 sets of DACs. The voltage sources with values weighted by 20 up to 27 are switched according to the data input so that the sum of the selected voltages gives the required analog voltage from the output driver.
P83Cx80; P87C380
The range of the output voltage is approximately 0 to 5 V. However, to fulfil some special requirement for current driving capability, a very minor reduction (0.2 to 0.4 V) of the output voltage range is acceptable. The DAC outputs are protected against short-circuits to VDDA and VSSA. To avoid the possibility of oscillation, capacitive loading at the DAC outputs should not exceed 10 pF. In reduced power modes like Idle mode and Power-down mode, the operation of the DACs can be disabled to save the power consumption. In that case, the outputs of the DACs are indeterminate. Figure 20 illustrates the block diagram of the DAC. 16.1 8-bit Data Registers for the DAC outputs (DACn; n = 0 to 3)
The DACs are individually programmed using an 8-bit word to select an output from one of 256 voltage steps. For VDDA = 5 V, the maximum output voltage of all DACs is 5 V and the resolution is approximately 17.6 mV (5 V/256). At power-on all DAC outputs are set to their lowest value: 00H (i.e. 0 V). The relevant SFRs for the DACs are described in Table 33 and 34.
Table 33 8-bit Data Registers for the DAC outputs (address E9H to ECH) 7 DACn.7 6 DACn.6 5 DACn.5 4 DACn.4 3 DACn.3 2 DACn.2 1 DACn.1 0 DACn.0
Table 34 Description of DACn bits BIT 7 to 0 SYMBOL DACn.7 to DACn.0 DESCRIPTION 8-bit data for the DAC; channel n (n = 0 to 3).
1997 Dec 12
39
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
handbook, full pagewidth
internal bus REFERENCE VOLTAGE/CURRENT GENERATOR
8
DATA LATCH (SFR ADDRESS E9H)
DATA LATCH (SFR ADDRESS EAH)
DATA LATCH (SFR ADDRESS EBH)
DATA LATCH (SFR ADDRESS ECH)
DAC0
DAC1
DAC2
DAC3
MGG050
DAC0
DAC1
DAC2
DAC3
Fig.22 Block diagram of the DAC.
1997 Dec 12
40
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
17 DISPLAY DATA CHANNEL (DDC) INTERFACE The monitor typically includes a number of user controls to set picture size, position, colour balance, brightness and contrast. Furthermore, to optimize some internal setting for different display modes, the timing characteristics should be acquired by the control side. For factory alignment, it is preferable to store the entire information in a non-volatile memory to facilitate production automation. Normally, monitors provide hardware control panels or a keypad to perform this control. However, it is now popular for these controls to go to the PC host. Therefore the communication between monitor and host becomes an issue. DDC1, DDC2B, DDC2B+ and DDC2AB (ACCESS.bus) emerge as a standard for monitor interface. 17.1
P83Cx80; P87C380
P83C880 is compliant to DDC1, DDC2B, DDC2B+ and DDC2AB (ACCESS.bus). They also conform to the detection sequence defined by VESA and ACCESS.bus Industry Group and identify the protocol which they are communicating with. A transmitter clocked by the incoming VSYNC is dedicated for DDC1 operation. An I2C-bus interface hardware logic forms the kernel of DDC2B and DDC2AB. An address pointer, DDCADR (address 9EH), with post increment capability is employed to serve DDC1, DDC2B, DDC2B+ and DDC2AB modes. The conceptual block diagram is illustrated in Fig.23.
Special Function Registers related to the DDC interface
Table 35 SFRs related to the DDC interface ADDRESS 9CH 9DH 9EH 9FH D8H D9H DAH DBH 17.1.1 SFR RAMBUF DDCCON DDCADR DDCDAT S1CON S1STA S1DAT S1ADR One extra I2C-bus interface is used to serve DDC2B, DDC2B+ and DDC2AB. Therefore S1CON, S1STA, S1DAT and S1ADR are just the copies of the corresponding registers in the general I2C-bus interface. Their usage is exactly the same. See Section 7.3.1. DDCCON, DDCADR and DDCDAT are mainly created for the DDC1 protocol; they are explained in Sections 17.1.1 to 17.1.3. REMARKS
DDC MODE STATUS AND DDC1 CONTROL REGISTER (DDCCON)
Table 36 DDC Mode Status and DDC1 Control Register (address 9DH) 7 - 6 EX_DAT 5 SWENB 4 - 3 DDC1_int 2 DDC1enable 1 SWH_int 0 M0
1997 Dec 12
41
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
Table 37 Description of DDCCON bits BIT 7 6 SYMBOL - EX_DAT Reserved. DESCRIPTION
P83Cx80; P87C380
This bit defines the size of the EDID data. It is related to the function of the post increment of the address pointer, DDCADR. When the upper limit is reached, the address pointer will wrap around to 00H. If EX_DAT = 1, the data size is 256 bytes. If EX_DAT = 0, the data size is 128 bytes; the addressing range for the EDID data buffer is mapped from 0 to 127, the rest (128 to 255) can still be used by the system. This bit indicates if the software/CPU is needed to take care of the operation of DDC1 protocol. If SWENB = 1, in DDC1 protocol, the CPU is interrupted during the period of the 9th transmitting bit so that the software service routine can update the hold register of the transmitter by moving new data from the appropriate area (it is not necessary to be the RAM buffer). This transferring must be done within 40 s. If SWENB = 0, the hold register of the transmitter will be automatically updated from the RAM buffer without the intervention of the CPU. Reserved. Interrupt request bit (002BH is assigned as the interrupt vector address). This bit is only valid in DDC1 protocol while software handling is enabled (SWENB = 1). This bit is set by hardware and should be cleared by software in an interrupt service routine. If DDC1 is fully under the hardware control (SWENB = 0), this bit can be ignored. If DDC1_int = 1, interrupt request is pending. If DDC1_int = 0, there are no interrupt request.
5
SWENB
4 3
- DDC1_int(1)
2 1
DDC1enable(1) DDC1 enable control bit. If DDC1enable = 1, DDC1 is enabled. If DDC1enable = 0, DDC1 is disabled (the activity on VCLK is ignored). SWH_int(1) Interrupt request bit (002BH is assigned as the interrupt vector address). This bit is used to indicate that DDC interface switches from DDC1 to DDC2 (i.e. the HIGH-to-LOW transition is observed on pin SCL1). This bit should be cleared by software in an interrupt service routine. If SWH_int = 1, interrupt request is pending. If SWH_int = 0, there is no interrupt request. DDC mode indication bit. If M0 = 0, DDC1 is set; if M0 = 1, DDC2 is set.
0 Note
M0(1)
1. These bits are R/W.
1997 Dec 12
42
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
17.1.2 ADDRESS POINTER FOR DDC INTERFACE REGISTER (DDCADR)
P83Cx80; P87C380
The bits of this register are all R/W. Table 38 Address Pointer for DDC Interface Register (address 9EH) 7 DDCADR.7 6 DDCADR.6 5 DDCADR.5 4 DDCADR.4 3 DDCADR.3 2 DDCADR.2 1 DDCADR.1 0 DDCADR.0
Table 39 Description of DDCADR bits BIT 7 to 0 SYMBOL DDCADR.7 to DDCADR.0 DESCRIPTION Address pointer with the capability of post increment. After each access to RAMBUF register (either by software or by hardware DDC1 interface), the content of this register will be increased by one. It is available both in DDC1, DDC2 (DDC2B, DDC2B+ and DDC2AB) and system operation.
17.1.3
DDC1 DATA TRANSMISSION REGISTER (DDCDAT)
Table 40 DDC1 Data Transmission Register (address 9FH) 7 DDCDAT.7 6 DDCDAT.6 5 DDCDAT.5 4 DDCDAT.4 3 DDCDAT.3 2 DDCDAT.2 1 DDCDAT.1 0 DDCDAT.0
Table 41 Description of DDCDAT bits BIT 7 to 0 SYMBOL DDCDAT.7 to DDCDAT.0 DESCRIPTION Data byte to be transmitted in DDC1 protocol.
1997 Dec 12
43
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
handbook, full pagewidth
7 SIO2 MONITOR ADDRESS S1ADR(DBH) SDA1 S1DAT(DAH) ARBITRATION LOGIC SHIFT REGISTER
1
0
SCL1
BUS CLOCK GENERATOR
CR2 ENS STA STO S1CON(D8H)
SI
AA CR1 CR0 INTERNAL BUS RAMBUF(9CH) RAMBUF
DDC2B/DDC2AB/DDC2B+ INTERFACE
SC4 SC3 SC2 SC1 SC0 S1STA(D9H)
0
0
0
DDC1/DDC2 DETECTION
DDC1 HOLD REGISTER DDCDAT(9FH) DDC1 TRANSMITTER
AUX-RAM BUFFER
ADDRESS POINTER VCLK INITIALIZATION SYNCHRONIZATION DDCADR(9EH)
-
EX_DAT
SWENB
-
DDC1_int
DDC1 enable
SWH_int
M0 (from S1CON) SI INT (interrupt vector 002BH)
MGG030
DDCCON(9DH)
Fig.23 DDC interface block diagram.
1997 Dec 12
44
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
17.2 Host type detection
P83Cx80; P87C380
The detection procedure conforms to the sequences proposed by "VESA Monitor Display Data Channel (DDC) specification". The monitor needs to determine the type of host system: * DDC1 or OLD type host * DDC2B host (host is master, monitor is always slave) * DDC2B+/DDC2AB (ACCESS.bus) host. The sequence of detection is described in the flow chart illustrated in Fig.24. The monitor where P83C880 resides is always both DDC1 and DDC2 compatible with DDC2 having the higher priority. The display (i.e. P83C880) shall start transmitting DDC1 signals whenever it is switched on and VSYNC is applied to it from the host for the first time. The display shall switch to DDC2 within 3 system clocks as soon as it sees a HIGH-to-LOW transition on the clock line (SCL), indicating that there are both DDC2 devices connected to the bus. Under that condition, the Mode flag M0 will be changed from the default setting logic 0 to logic 1.
Accordingly, the interrupt will be invoked by setting flag SWH_int (DDCCON.1) as HIGH (this flag must be cleared by the interrupt service routine). This procedure will cause a transmission error. However, both the display and the host shall have error detection and a method to recover from the temporary transmission errors. Figure 24 illustrates the concept and interaction between the monitor and the host. After power-on, the DDC1enable bit (DDCCON.2) is set by software, setting the monitor as a DDC1 device. Therefore, the Mode flag M0, is set as logic 0. Following VSYNC as clock, the monitor (i.e. P83C880) will transmit EDID data stream to the host. However, if DDC2 clock (SCL clock) is present, the monitor will be switched to DDC2B device with the Mode flags setting as logic 1. Software will determine whether it is a DDC2B, DDC2B+, or DDC2AB protocol.
1997 Dec 12
45
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
handbook, full pagewidth
MONITOR POWER-ON
COMMUNICATION IS IDLE
IS VSYNC PRESENT?
NO
EDID SENT CONTINUOUSLY USING VSYNC AS CLOCK
IS DDC2 CLOCK PRESENT?
NO
YES STOP SENDING OF EDID SWITCH TO DDC2 COMMUNICATION MODE (1) DDC2 COMMUNICATION IS IDLE. MONITOR IS WAITING FOR A COMMAND
HAS A COMMAND BEEN RECEIVED?
NO
YES
NO
IS DDC2B+/DDCAB2 COMMAND DETECTED? YES IS MONITOR DDC2B+/DDCAB2 CAPABLE? YES
NO
IS COMMAND DDC2B COMMAND? YES RESPOND TO DDC2B COMMAND
NO
RESPOND TO DDC2B+/DDCAB2 COMMAND
MGG031
(1) Once the monitor switches from DDC1 mode to DDC2 mode it will remain in DDC2 mode for the duration of that power-on period.
Fig.24 Host type detection.
1997 Dec 12
46
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
17.3 DDC1 protocol
P83Cx80; P87C380
The DDC1 is a primitive interface, but adopted by many monitor models and PC hosts. It is a point-to-point interface. The monitor is always set to `Transmit only' mode. In the initialization phase, 9 clock cycles on the VCLK pin will be given for the internal synchronization. During this period, the SDA pin will be kept in the high-impedance state. By default, bit `DDC1enable' is reset as logic 0. It is advised to move the EDID data to the RAM buffer before enabling DDC1. To activate the DDC1 interface, DDC1enable flag is set to logic 1 and it is taken as granted that Mode flag M0 is set at logic 0. If SWENB is kept at the default value logic 0, the RAM buffer will be tied to the DDC1 protocol. The allocated size from the RAM buffer is decided by the flag EX_DAT. If EX_DAT is LOW, only 128 bytes are reserved to store DDC1 EDID data. The upper part (locations 128 to 255) is still available to the system. If EX_DAT is HIGH, the entire 256 bytes of the RAM buffer are dedicated to the usage of DDC1 operation. The hardware mechanism will automatically move new data from the defined RAM buffer to the hold register of the transmitter with the aid of the address pointer DDCADR. Within the range of DDC1 RAM buffer, the function of the post increment is executed. If the upper limit is reached, the address pointer DDCADR will wrap around to 00H. However, if EX_DAT = LOW, the lower part is occupied by the DDC1 operation and the upper part is still free to the system. Nevertheless, the effect of the post increment just applies to the part related to the DDC1 operation. In other words, the system program is still able to address the locations from 128 to 255 in the RAM buffer through the MOVX command but without the facility of the post increment; e.g. in case EX_DAT = LOW and SWENB = LOW, the system program might read one data byte from address 200 of the RAM buffer by the following procedure: MOV R0, #200; MOVX A, @R0. The address pointer DDCADR is tied to the DDC1 transmitter here. To avoid the interference to the content of DDCADR, it has to address the RAM buffer through the MOVX command. While EX_DAT = HIGH, the entire RAM buffer is covered by the pointing range of the address pointer DDCADR, with the capability of the post increment; no matter whether the access is done by DDC1 related hardware (SWENB = 0) or software (SWENB = 1). If SWENB is set at logic 1, then after the valid synchronization, the DDC1 interrupt will be invoked (interrupt vector address 002BH). The service routine should fill the hold register DDCDAT (SFR address 9FH) with the first data byte either from the internal ROM (part 1997 Dec 12 47
of the system ROM) or from the RAM buffer. In the latter case, the address pointer DDCADR will provide the benefit of the post increment for the service routine to read/write the DDC1 EDID data area. This action must be finished within 40 s (40 machine cycles in 12 MHz system clock). DDC1_int flag must be cleared by software before it returns from service routine. On the rising edge of the 10th clock cycle, the device will output the first valid data bit which should be the most significant bit of a byte. The following data is also transmitted on the SDA pin in 8 bits per byte format. Each byte is followed by a 9th clock pulse during which time SDA is left high-impedance and either the hardware mechanism (SWENB = 0) or the service routine (SWENB = 1) will update the hold register. The data bit is output on the rising edge of VCLK, the most significant bit first. The address pointer is initialized at 00H. After writing a data byte to the hold register through hardware or software, it will be incremented by one automatically. If the address reaches 127 (EX_DAT = 0) or 255 (EX_DAT = 1) the address pointer will wrap around to the first location: 00H. Nevertheless, it is possible for CPU (in software mode, i.e. SWENB = 1) to write any desired address to the address pointer to proceed random access. The transaction in DDC1 protocol is shown in Fig.25. If DDC1 hardware mode is used, the following DDC1 operation steps are recommended: 1. Reset DDC1enable (by default DDC1enable is cleared to LOW after power-on reset). 2. Set SWENB to HIGH. 3. Depending on the data size of EDID data, set EX_DAT to LOW (128 bytes) or HIGH (256 bytes). 4. Use substantial moving commands (DDCADR, RAMBUF involved) to move the entire EDID data to RAM buffer. 5. Reset SWENB to LOW. 6. Reset DDCADR to 00H. 7. Set DDC1enable to HIGH enabling the DDC1 hardware; during the synchronization phase (the first 9 VCLK clocks) the first data byte will be loaded into the shift register of the transmitter through the hold register.
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
handbook, full pagewidth
DDC1_INT DDC1 enable
00
01
11
01
11
01
SCL
SDA
High Z
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT BIT 0 High Z 7
VCLK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
tsu(DDC1)
tVCLKH tVCLKL
tDOV
MGG032
Fig.25 Transmission protocol in DDC1 interface.
17.4
DDC2B protocol
According to the DDC2B specification: * A0H (for write mode) and * A1H (for read mode), are assigned as the default address of monitors. The reception of the incoming data in write mode or the updating of the outgoing data in read mode should be finished within the specified time limit. However, it is not necessary for EDID data to be stored on-chip. It is also possible to have access to the external EEPROM/ROM through another set of I2C-bus interface and pre-store those data in the RAM buffer. If software on the slave side cannot react to the master in time, based on I2C-bus protocol, SCL pin can be stretched LOW to inhibit the further action from the master. The transaction can be proceeded in either byte or burst format.
The DDC2B construction is based on the Philips I2C-bus interface. However, in the level of DDC2B, PC host is fixed as the master and the monitor is always regarded as the slave. Both master and slave can be operated as a transmitter or receiver, but the master device determines which mode is activated. For details of the I2C-bus interface, please refer to the Philips publication "The I2C-bus and how to use it" ordering number 9398 393 40011 and/or the "Data Handbook IC20". In the P83C880, one more pair of I2C-bus pins SCL1, SDA1 and an I2C-bus hardware interface logic are dedicated to perform DDC2B/DDC2B+/DDC2AB protocols. The built-in address pointer mentioned in Section 17.3 can be used to speed up the processing of service routines for the access of the internal ROM or a dedicated RAM buffer.
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
17.5 DDC2AB/DDC2B+ protocol
P83Cx80; P87C380
DDC2AB/DDC2B+ is a superset of DDC2B. Monitors that implement DDC2AB/DDC2B+ are full featured ACCESS.bus devices. Essentially, they are similar to DDC2B. The I2C-bus interface forms the fundamental layer for both protocols. However, in DDC2AB/DDC2B+ the default address for monitors is assigned to 6EH instead of A0H and A1H in DDC2B. Monitors and hosts can play both the roles of master and slave. Under this kind of protocol, it is easy to extend the support for hosts to read VESA Video Display Information Format (VDIF) and remotely control monitor functions. The read/write protocols can be the same as described in Section 17.4.
Nevertheless, the command/information sequence between host and monitor must conform to the specification of ACCESS.bus. Timing rules specified in ACCESS.bus such as maximum response time to RESET message (<250 ms) from host, maximum time to hold SCL LOW (<2 ms) etc., can be satisfied through software checks and built-in timers such as Timer 0 and Timer 1 in the P83C880. In DDC2AB/DDC2B+ the monitor itself can act as a master to activate the transaction. The default address assigned for the host is 50H. Figure 26 shows the overview and relationship between software and the existing I2C-bus hardware for the DDC interface.
handbook, full pagewidth
DDC INTERRUPT VECTOR ADDRESS (002BH)
CHECK MODE FLAG IN DDCCON SWENB = 1 MODE = 1 MODE = 0
DDC2B+/DDC2AB COMMAND RECEIVED
DDC2B COMMAND RECEIVED
DDC2B+/DDC2AB UTILITIES
DDC2B UTILITIES
SWENB = 0
I2C-BUS SERVICE ROUTINES
DDC1 UTILITIES
I2C-BUS INTERFACE (HARDWARE)
DDC1 TRANSMITTER (HARDWARE)
MGG035
Fig.26 The conceptual structure of the DDC interface.
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
17.6 RAM buffer for the system and DDC application
P83Cx80; P87C380
The architecture of the RAM buffer is set up in a flexible configuration to use the RAM resource to a maximum. In principle the RAM buffer can be shared as system or DDC RAM buffer. The relationship among those applications is arranged as shown in Table 42. Table 42 Relation between system RAM and DDC RAM AUX RAM 0 TO 127 MODE DDC1 EX_DAT SWENB 0 0 1 1 DDC2 0 1 Notes 1. Read/write through MOVX instruction might conflict with the access from DDC1 hardware. So the access from CPU by using MOVX instruction is forbidden. 2. READ/WRITE through DDCADR and RAMBUF registers has the conflicting problem also. Even the content of DDCADR, which should be employed by DDC1 hardware, will be damaged. So it is inhibited to use this type of access. 3. If DDCADR reaches 127 it will automatically wrap around to 0 after the access is done. 4. The access conflict can be avoided because DDC1 access is done by the interrupt service routine. However, the EDID transferring from the RAM buffer should be finished within 40 s. 5. If DDCADR reaches 255 it will automatically wrap around to 0 after the access is done. 18 I2C-BUS INTERFACE The P83C880 has a software I2C-bus interface that can be used in master mode. Full details of the I2C-bus are given in the 80C51 family "Data Handbook IC20" and/or the document "The I2C-bus and how to use it" (ordering number 9398 393 40011). The I2C-bus interface lines SDA and SCL share the same pins as Port 1 lines P1.1 and P1.0 respectively; selection is done via the S1E bit in SFR DFCON (address C0H). 0 1 0 1 1 1 DDC2 EDID data DDC1 EDID data NORMALLY RESERVED FOR NOTE 1, 2 and 3 3 and 4 1 and 2 4 3 - DDC1 EDID data - DDC2 EDID data AUX RAM 128 TO 255 NORMALLY RESERVED FOR - AVAILABLE FOR system access - system access - 2 - 1, 2 and 5 4 and 5 - 5 NOTE
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
19 HARDWARE MODE DETECTION Due to the many restrictions for mode detection via software, a hardware mode detector is introduced in the P83C880. This feature has the following advantages: * Fast enough to react on any mode change. * Possibility to detect the polarity of HSYNC without extra input pin. * Higher accuracy to measure the HSYNC and VSYNC frequency * Relieves the CPU and valuable timers/counters in the microcontroller from lengthy mode detection * In reduced power modes, e.g. Idle mode, the mode detection is still active. Apart from the above mentioned benefits, some extra features can be achieved through hardware mode detection. The composite sync separation can be done while mode detection continues. The various formats of HSYNC and VSYNC output pulses are provided to fit into different applications. Since the information of the operational modes defined in Device Power Management Signalling (DPMS) for monitors is embedded in HSYNC and VSYNC, the mode 19.1.1
P83Cx80; P87C380
detector is also able to recognize the operational mode and generate the fixed free running frequency for HSYNC and VSYNC in some specific modes like stand-by, suspend and power-off. Two display patterns, the white and the cross hatch, can be displayed for the self test in the free running mode. More on Device Power Management Signalling (DPMS) will be explained in Chapter 20, "Power management". 19.1 Special Function Register for mode detection and sync separation
There are 4 SFRs related to mode detection and sync separation: MDCST (SFR address F8H); HFHIGH (SFR address FCH); VFHIGH (SFR address FDH) and VFLHFL (SFR address FEH). Five SFRs are applied for the output pulse generation of HSYNC and VSYNC and the display pattern generation for the self test: HFP (SFR address F6H); HFPOPW (SFR address F7H); VFP (SFR address F9H); VFPOPW (SFR address FAH) and PULCNT (SFR address FBH). These SFRs are described in detail in Section 19.1.1 to 19.1.9.
MODE DETECTION/SYNC SEPARATION CONTROL AND STATUS REGISTER (MDCST)
Table 43 Mode Detection/sync separation Control and Status Register (SFR address F8H) 7 MARCH 6 CHREQ 5 XSEL 4 HSEL 3 Hpres 2 Vpres 1 Hpol 0 Vpol
Table 44 Description of MDCST bits BIT 7 SYMBOL MARCH DESCRIPTION Mode detection enable. If MARCH = 1, mode detection is enabled. If MARCH = 0, mode detection is disabled. Default value MARCH = 1 to guarantee that mode detection is automatically executed after power-on reset. Polarity or frequency change. If CHREQ = 1 then the polarity or frequency change happened. The polarity or frequency is detected after a CHREQ HIGH-to-LOW transition, because the mode change becomes stable after the CHREQ HIGH-to-LOW transition. Indicates if the clock used for the mode detection and the pulse generation is 12 x fclk. If XSEL = 1, the internal clock is12 x fclk. If XSEL = 0 the internal clock is equal to fclk. Indicates the horizontal sync input coming from HSYNCin (pin HSYNCin/PROG) or CSYNCin (pin CSYNCin/P1.6). If HSEL = 1, CSYNCin is the input pin. If HSEL = 0, HSYNCin is the input pin. Indicates the presence of HSYNC. If Hpres = 1, HSYNC is present. If Hpres = 0, HSYNC is not present.
6
CHREQ
5 4
XSEL HSEL
3
Hpres
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
BIT 2 1 SYMBOL Vpres Hpol DESCRIPTION
P83Cx80; P87C380
Indicates the presence of VSYNC. If Vpres = 1, VSYNC is present. If Vpres = 0, VSYNC is not present. Indicates the polarity of HSYNC. If Hpol = 0, polarity is positive (active HIGH; i.e. HIGH at horizontal retracing period). If Hpol = 1, polarity is negative (active LOW; i.e. LOW at horizontal retracing period). Indicates the polarity of VSYNC. If Vpol = 0, polarity is positive (active HIGH; i.e. HIGH at vertical retracing period). If Hpol = 1, polarity is negative (active LOW; i.e. LOW at vertical retracing period).
0
Vpol
19.1.2
HORIZONTAL PERIOD COUNTING HIGH-BYTE REGISTER (HFHIGH)
Table 45 Horizontal Period Counting High-byte Register (SFR address FCH) 7 HF.11 6 HF.10 5 HF.9 4 HF.8 3 HF.7 2 HF.6 1 HF.5 0 HF.4
Table 46 Description of HFHIGH bits BIT 7 to 0 SYMBOL HF.11 to HF.4 DESCRIPTION Indicate the high byte of the value counted by mode detector for 4 horizontal scanning periods.
19.1.3
VERTICAL PERIOD COUNTING HIGH-BYTE REGISTER (VFHIGH)
Table 47 Vertical Period Counting High-byte Register (SFR address FDH) 7 VF.11 6 VF.10 5 VF.9 4 VF.8 3 VF.7 2 VF.6 1 VF.5 0 VF.4
Table 48 Description of VFHIGH bits BIT 7 to 0 SYMBOL VF.11 to VF.4 DESCRIPTION Indicate the high byte of the value counted by mode detector for 1 vertical field/frame period.
19.1.4
VERTICAL AND HORIZONTAL PERIOD COUNTING LOW-NIBBLES REGISTER (VFLHFL)
Table 49 Register containing the low nibbles of the Horizontal and Vertical Period Counting (SFR address FEH) 7 VF.3 6 VF.2 5 VF.1 4 VF.0 3 HF.3 2 HF.2 1 HF.1 0 HF.0
Table 50 Description of VFLHFL bits BIT 7 to 4 3 to 0 SYMBOL VF.3 to VF.0 HF.3 to HF.0 DESCRIPTION Indicate the low nibble of the value counted by mode detector for 1 vertical field/frame period. Indicate the low nibble of the value counted by mode detector for 4 horizontal scanning periods.
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
19.1.5 HORIZONTAL FREE RUNNING FREQUENCY/PERIOD BYTE REGISTER (HFP)
P83Cx80; P87C380
Table 51 Horizontal free running Frequency/Period Register byte Register (SFR address F6H) 7 HFP9 6 HFP8 5 HFP7 4 HFP6 3 HFP5 2 HFP4 1 HFP3 0 HFP2
Table 52 Description of HFP bits BIT 7 to 0 SYMBOL HFP9 to HFP2 DESCRIPTION Indicate the upper byte of the 10 bits for programming the free running HSYNC output pulse.
19.1.6
HORIZONTAL FREE RUNNING FREQUENCY/PERIOD AND PULSE WIDTH REGISTER (HFPOPW)
Table 53 Horizontal free running Frequency/Period and Pulse Width Register (SFR address F7H) 7 VSEL 6 HFP1 5 HFP0 4 HOPW4 3 HOPW3 2 HOPW2 1 HOPW1 0 HOPW0
Table 54 Description of HFPOPW bits BIT 7 VSEL SYMBOL DESCRIPTION Indicates whether the internal vertical sync is coming from the external VSYNC input pin (VSYNCin/OE) or separated from the composite signal. If VSEL = 0, vertical sync coming from the external VSYNC input pin. If VSEL = 1, vertical sync separated from the composite signal. Indicate the lower two of the 10 bits for programming the free running horizontal output pulse. Indicate the horizontal output pulse width.
6 to 5 4 to 0 19.1.7
HFP1 to HFP0 HOPW4 to HOPW0
VERTICAL FREE RUNNING FREQUENCY/PERIOD BYTE REGISTER (VFP)
Table 55 Vertical free running Frequency/Period byte Register (SFR address F9H) 7 VFP9 6 VFP8 5 VFP7 4 VFP6 3 VFP5 2 VFP4 1 VFP3 0 VFP2
Table 56 Description of VFP bits BIT 7 to 0 SYMBOL VFP9 to VFP2 DESCRIPTION Indicate the upper byte of the 10 bits for programming the free running vertical output pulse.
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
19.1.8
P83Cx80; P87C380
VERTICAL FREE RUNNING FREQUENCY/PERIOD AND PULSE WIDTH REGISTER (VFPOPW)
Table 57 Vertical free running Frequency/Period and Pulse Width Register (SFR address FAH) 7 - 6 - 5 VFP1 4 VFP0 3 VOPW3 2 VOPW2 1 VOPW1 0 VOPW0
Table 58 Description of VFPOPW bits BIT 7 to 6 5 4 3 to 0 19.1.9 - VFP1 VFP0 VOPW3 to VOPW0 SYMBOL Reserved. Indicate the lower two bits of the 10 bits for programming the free running vertical output pulse. Indicate the vertical output pulse width. DESCRIPTION
PULSE GENERATION CONTROL REGISTER (PULCNT)
Table 59 Pulse generation Control Register (SFR address FBH) 7 CLMPEN 6 PATTYP 5 VPG 4 PVSI 3 HPG1 2 HPG0 1 FBPO 0 PHSI
Table 60 Description of PULCNT bits BIT 7 SYMBOL CLMPEN DESCRIPTION Clamping pulse output (CLAMP) enable. If CLMPEN = 1, pin PWM8/CLAMP/P3.0 is switched to the CLAMP output. If CLMPEN = 0, the CLAMP function is disabled. The CLAMP function always overrides other alternative functions such as PWM8 and P3.0. Basic display patterns selection. If PATTYP = 0, the white display pattern is selected. If PATTYP = 1, the cross hatch display pattern is selected. Vertical pulse output modes selection. If VPG = 0, a free running vertical sync pulse signal is selected. If VPG = 1, a vertical substitution pulse signal is selected. Vertical output pulse polarity selection. If PVSI = 0, the positive polarity is selected. If PVSI = 1, the negative polarity is selected. Horizontal pulse output modes selection; see Table 61. The clamp pulse at the back porch or at the front porch selection. This bit is only valid when CLMPEN is set HIGH. If FBPO = 1, the horizontal back porch clamp pulse is selected. If FBPO = 0, the horizontal front porch clamp pulse is selected. Polarity of the horizontal and clamping output pulse indication. If PHSI = 0, the positive polarity is selected. If PHSI = 1, the negative polarity is selected.
6
PATTYP
5
VPG
4 3 to 2 1
PVSI HPG1 to HPG0 FBPO
0
PHSI
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
Table 61 Horizontal pulse output modes HPG1 HPG0 0 0 1 1 0 1 0 1 free running horizontal sync pulse signal horizontal substitution pulse signal reserved MODES
P83Cx80; P87C380
the incoming horizontal sync is followed and delivered out but the horizontal substitution pulse is disabled, while the incoming HSYNC is missing
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19.2
dbook, full pagewidth
1997 Dec 12
HSYNC_P CLAMP 12 12 10 FBPO HPG1 to HPG0 VFP9 to VFP0 V Vpres Vper PVSI 12 12 10 Vpol Vper VOPW3 to VOPW0 VPG 4 PHSI 5 Hpres H SYNC SEPARATION Hpol Hper H-MODE DETECTION MUX H-PULSE GENERATOR HSYNCout
HSEL
HSYNCin
MUX
Philips Semiconductors
System description
CSYNCin
HSYNC POLARITY CORRECTION
Hpol
12 Hper Hper HFP9 to HFP0 HOPW4 to HOPW0
Vpol
VSYNCin
VSYNC POLARITY CORRECTION
V-MODE DETECTION
V-PULSE GENERATOR
MUX
VSYNCout
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
56
Hpres Hper Vpol 12 12 Vper Vper or Vpol change Vpres Hpol Hper or Hpol change HFP9 to HFP0 VFP9 to VFP0 controls 10 10 FOSH CAPTURE REGISTERS DIV 76 FOSV MODE DETECT AND PULSE GENERATION CONTROL microcontroller core CHREQ (Change Interrupt Request) microcontroller core
MGG036
fclk
DIV 2
XSEL
P83Cx80; P87C380
Product specification
Fig.27 Block diagram of the hardware mode detection and pulse generation.
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
19.2.1 CLOCK PRESCALER 19.2.3
P83Cx80; P87C380
VERTICAL POLARITY CORRECTION
To reach the required 12 bit accuracy and the reasonable crystal clock frequency, the line time of 4 consecutive lines is measured (see Section 19.2.5). Doing so the maximum crystal clock frequency is: 2 12 x f H(min) Hz f clk ----------------------------- = 15.36 M 4 From the calculation above it is clear that there will be no overflow if fclk is 10 or 12 MHz. However, for a 16 or 24 MHz crystal fclk has to be divided by a factor of 2 to get a correct clock frequency FOSH for the horizontal part of the mode detection. If fclk used is 10, 12 or 16 MHz then FOSH will be respectively 10, 12 or 8 MHz. The same holds for the vertical part of the mode detection. Here the minimum vertical sync frequency fV(min) = 40 Hz, so the maximum clock frequency to avoid overflow in a 12-bit counter, equals: 12 FOSV 2 x f V(min) = 163.84 kHz To get a maximum accuracy without overflow the clock of the horizontal section FOSH, should be prescaled down to this value of FOSV. Thus the scale factor should be at
3 FOSH ( max ) 12 x 10 k Hz least: n ------------------------------ = ---------------------------------- = 73.2 163.84 kHz 163.84 kHz
The purpose of the vertical polarity correction is similar to the horizontal polarity correction. However, it takes a longer time to get the correct result after power-on or a timing mode change because at least 5 frames are needed to stabilize Vper from the input sync signals. 19.2.4 VERTICAL SYNC SEPARATION
This function will separate the vertical sync out of the composite sync. To do so the change in polarity during VSYNC interval can be utilized to extract VSYNC as shown in Fig.28. The differentiated sync pulse derived from HSYNC_P is used to reset an 8-bit upcounter. At 14 of the line time the level of the incoming sync at that moment is clocked into the last D flip-flop. Be aware that 1 of the line period equals 1 of parameter Hper because 4 16 Hper is calculated based on 4 consecutive lines. Due to the fact that the differentiator reacts upon every LOW-to-HIGH transition even an interlaced composite sync will be separated correctly. Note further that the sync separation is taken from signal HSYNC_P which is processed by the Horizontal Polarity Correction circuit but not necessary with the fixed polarity. As a result the polarity of the separated vertical sync Vsep will vary with the incoming composite signal, and in case no composite sync is present the level will be LOW. According to this algorithm, Vsep will be always 14HSYNC period shift to the original VSYNC window. The 8-bit counter in Fig.28 is stopped at its maximum of FFH, otherwise it will start again from zero which results in a wrong enable pulse for the D flip-flop. All kinds of composite sync input shown in Chapter 27 can be dealt with by this function. There are 6 types of composite sync waveforms which can be accepted by the sync processor (see Fig.39).
Take n = 76 as a suitable scale factor as shown in Fig.23. Table 62 Clock frequencies fclk (MHz) 10 12 16 19.2.2 FOSH (MHz) 10 12 8 FOSV (MHz) 131.6 157.9 105.3
HORIZONTAL POLARITY CORRECTION
In order to simplify the processing in the following stages, the HSYNC polarity correction circuit is able to convert the input sync signals to positive polarity signals in all situations. However, be aware that this correction is achieved by the aid of Hpol and Hper signals. Hpol and Hper are only settled down in several horizontal scanning lines (61 lines, if fHSYNC goes up) or a few milliseconds (worst case 1.2 ms, if fHSYNC becomes inactive) after power-on or timing mode change.
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
handbook, full pagewidth
P83Cx80; P87C380
HSYNC_P DIFFERENTIATOR R E FOSH 8-BIT COUNTER Q7 to Q0 COMPARATOR FOR SYNC SEPARATION DIV 16
MGG037
D E D-FF Q Vsep
Hper
Fig.28 Vertical sync separator.
19.2.5
HORIZONTAL MODE DETECTION
This function block determines the following 4 parameters: Hper, Hpol, Hpres and Hcha. The functional block diagram is shown in Fig.29. The 12-bit counter for the determination of the horizontal period has a synchronous reset and will be reset by the prescaled and differentiated horizontal pulse HSYNC_P, coming from the horizontal prescaler, or in case the counter reaches the value FF0H as defined by the comparator. The latter situation will occur if no sync pulses are coming in or if the frequency of the incoming sync pulses is too low. The 12-bit register, that will store the 4 line time period, is only enabled if the signal HENA is HIGH.
19.2.5.1
Parameter Hper
Based on this configuration, the resulting accuracy for Hper will be: 100% x f H 100% Accuracy in H = ------------------------------------------------------------------ = -------------------------4 x FOSH (horizontal counter value) Table 63 Accuracies XTAL (fclk) (MHz) 10 12 16 10 12 8 FOSH (MHz) ACCURACY IN H AT 30KHZ (%) 0.075 0.063 0.094 ACCURACY IN V AT 50HZ (%) 0.038 0.032 0.048
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
A 12-bit counter is used to measure the frequency of HSYNC. Every 4 HSYNC periods are measured and compared with the previous locked HSYNC frequency; the counter is reset every 4 HSYNC periods. The base clock 1 to the counter is ------------------ = 83 ns for a 12 MHz system 12 MHz clock. If the new HSYNC frequency is larger than the previous HSYNC frequency, there is a 4-bit counter to avoid the noise or the temporary frequency shift. When the 4-bit counter counts up to 15 for the comparison Hfreq(new) > Hfreq(previous), then the mode change interrupt is issued. The time from mode change to interrupt issued is approximately 4 x Hperiod(new) x 15 or (4 x Hperiod(new) x 14) + n x Hperiod(previous)), where n = 1, 2 or 3. If the new HSYNC frequency is not in the static state and is smaller than the previous HSYNC frequency, the time from mode change to interrupt issued is approximately (4 x Hperiod(new) x 3) - (n x Hperiod(previous)), where n = 1, 2, 3 or 4. The static state is considered as the state where the 12-bit counter, for measuring the HSYNC frequency, reaches 4080. For a 12 MHz system clock, the static state is equal to 1 1 -------------------------------- = ----------------------- = 11.8 kHz . 4080 84660 ns 83 ns x -----------4 If the input HSYNC frequency is less than 11.8 kHz, it will be regarded as static state. A 2-bit counter is used to avoid the noise or the temporary shift. When the 2-bit counter counts up to 3 for the comparison `static state' < Hfreq(new) < Hfreq(previous), then the mode change interrupt is issued. Table 64 Hysteresis in the Hpres detection XTAL (fclk) (MHz) 10 12 16 10 12 8 FOSH (MHz) 9.804 11.765 7.843 Hfreq1 (MHz) 9.921 11.905 7.937
P83Cx80; P87C380
When the new input HSYNC is changed to a static state, the HSYNC frequency counter reaches 4080. In order to have a faster response of the mode change interrupt, the 2-bit counter is not used and the mode change interrupt is issued immediately. The time from mode change to interrupt issued is approximately ((4080 + 5) x 83 ns) - (n x Hperiod(previous)), where n = 1, 2, 3 or 4.
19.2.5.2
Parameter Hpres
The presence indicator Hpres, as stored in the SR flip-flop, contains some hysteresis, as required due to the two threshold settings in the comparator. The SR flip-flop will be set, indicating that no active sync (or sync with a too low frequency) is coming in if the counter reaches a value of FF0H (4080 decimal). The corresponding horizontal sync frequency is: 4 x FOSH 4 x FOSH f H = Hfreq1 = ------------------------------------------- = -------------------------( Counter value ) 4080 The SR flip-flop will be reset, indicating that an active sync is present, if the counter reaches a value lower than FC0H (4032 decimal). The corresponding horizontal sync frequency is: 4 x FOSH 4 x FOSH f H = Hfreq2 = ------------------------------------------- = -------------------------( Counter value ) 4032 The hysteresis result, Hysteresis = ( Hfreq1 - Hfreq2 ) Hfreq1 , is shown in Table 64.
Hfreq2 (MHz) 1.2 1.2 1.2
HYSTERESIS (%)
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59
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Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
19.2.5.3 Parameter Hpol 19.2.5.4
P83Cx80; P87C380
Parameter Hcha
The mode change interrupt will be issued after 36 to 40 periods of the HSYNC when the polarity is changed from negative to positive. The polarity indicator Hpol will be changed from a logic 1 to a logic 0. The mode change interrupt will be issued after the 60 periods of the HSYNC when the polarity is changed from positive to negative. The Hpol will be changed from a logic 0 to a logic 1. A logic 0 represents a positive polarity and a logic 1 represents a negative polarity.
If Hcha is set to HIGH indicating that the period time has changed for a long period, the Hper and Hpres will be updated. If the measured period time has become stable then the two counters will start to count down and the HENA signal is set to LOW again, thereby disabling the register Hper and the SR flip-flop for Hpres parameter.
handbook, full pagewidth
HENA Hres HSYNC_P R Q 11 to Q0 12-BIT COUNTER FOSH D11 to D0 12-BIT E REGISTER Q11 to Q0 Hcnt Hlow Hper CHANGE DETECTOR Hhgh MODE CHANGE STABILIZATION AND COMPARISON CIRCUIT
FOSH
S
Q SR-FF
Hper FOSH Hpres
MGG038
Hcha
R HSYNC Hper and Hpol DECISION CIRCUIT D E D-FF DIV 16 FOSH
Q
Q
Hpol
Fig.29 Horizontal mode detection.
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
19.2.6 VERTICAL MODE DETECTION
P83Cx80; P87C380
To detect the vertical mode parameters Vper, Vpol and Vpres, a circuit can be used which is almost similar to that for the horizontal mode detection. The only difference is that now the period time of one frame (instead of 4 lines) is measured. The presence indication for the vertical sync also contains a hysteresis of about 1.2%. The formula to calculate the hysteresis is also similar to the condition of HSYNC processing. A 12-bit counter is used to count the clock number during one frame. Again FF0H (4080 decimal) and FC0H (4032 decimal) are taken as the threshold for Vfreq1 and Vfreq2 respectively, but the clock FOSV = FOSH/76. Vfreq1, Vfreq2 and Hysteresis are calculated as follows: FOSV FOSH f V = Vfreq1 = ------------------------------------------- = ------------------------( Counter value ) 76 x 4080 FOSV FOSH f V = Vfreq2 = ------------------------------------------- = ------------------------( Counter value ) 76 x 4032 Table 65 Hysteresis in the Vpres detection (fclk) (MHz) 10 12 16 10 12 8 FOSH (MHz) 32.25 38.70 25.80
The hysteresis result, Hysteresis = ( Vfreq1 - Hfreq2 ) Hfreq1 , is shown in Table 64. If the new VSYNC frequency is larger than the previous VSYNC frequency, the time from mode change to interrupt issued is approximately from ((Vperiod(new) x 2) + Vperiod(previous)) to (Vperiod(new) x 3). If the new VSYNC frequency is not in the static state and is smaller than the previous VSYNC frequency, the time from mode change to interrupt issued is approximately from Vperiod(new) to Vperiod(new) x 2. If the new VSYNC frequency is in the static state, the time from mode change to interrupt issued is approximately from (4080 x 6.3 us) - Vperiod(previous) to 4080 x 6.3 s.
Vfreq1 (MHz) 32.63 39.16 26.11
Vfreq2 (MHz) 1.2 1.2 1.2
HYSTERESIS (%)
The polarity can be measured by looking to the level of the input sync at 14 of the frame time. The mode change in vertical the frame period will be detected if there is a change for a longer time than 3 frame periods. The accuracy of Vper can calculated by the following formula: 100% x f V 100% Accuracy in V = ----------------------------------------------------------- = ------------------------(vertical counter value) ( FOSV ) 100% x 76 x f V = -------------------------------------( FOSH ) The hysteresis results and the accuracy of Vper are shown in Table 63. 19.2.7 HORIZONTAL PULSE GENERATOR
2. A pulse starting at the beginning of the input horizontal sync but now with a fixed length, or a substitution pulse (with fixed length). 3. A free running sync pulse. 4. The same pulse as the input horizontal sync. The substitution pulse is inhibited even if HSYNC is missing. To be able to generate a substitution pulse the down counter, depicted in Fig.23, is loaded at each incoming sync with a period time just a bit longer than the measured Hper. If now normal syncs are present then the counter will be loaded just before it reaches 000H. Therefore the counter will not generate a pulse (in Fig.23, HPST remains LOW). However, if a sync pulse is missing the counter will reach 000H and generates a substitution pulse, HPST. At the same time it will load itself again for the next run. To generate free running pulses the only thing to do is to load the down counter with the parameter HFP and to stop the load pulses coming from the input sync, HSYNC_P. So, the signal HPST is either a free running pulse or a pulse in case an input sync is missing.
Through the control flags, HPG1 and HPG0, the horizontal pulse generator is able to generate the HSYNCout signal with the following formats: 1. The same pulse as the input horizontal sync, or a substitution pulse (with a fixed length) in case of a missing sync pulse. 1997 Dec 12 61
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Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
The 5-bit down counter is used to generate a pulse with pulse width tW(H). As shown in Fig.23, the SR flip-flop will be set by either HPST (free running/missing sync pulse) or by the leading or trailing edge of the incoming sync pulse, HSYNC_P. In the same way the SR flip-flop will be reset by either the end of the incoming sync pulse or by the pulse width counter.
P83Cx80; P87C380
If necessary (HPG1, HPG0: 1, 1), the substitution pulse can be suppressed and only the incoming HSYNC pulse will be delivered out. The frequency of the free running FOSH pulse is: f H(free) = --------------Hfp The pulse width of the free running mode is: tW(H) = TFOSH x (HOPW<4:0>)
handbook, full pagewidth
'0' COMPARATOR HSYNC_P HFP Hper DATA LOAD DECISION D9..0 L DOWN COUNTER Q9..0
HPST
FOSH PHSI HPG1 to HPG0 PULSE RISE/FALL GENERATOR S R Q SR-FF Q HSYNCout
HOPW FOSH
PULSE WIDTH GENERATOR
MGG039
Fig.30 Horizontal pulse generator.
19.2.8
VERTICAL PULSE GENERATOR
19.2.9
CAPTURE REGISTERS
The clock used in this vertical pulse generator must be switchable between FOSV (needed to generate missing sync pulses) and HPST (free running syncs from the horizontal pulse generator) needed in the free running mode. In the latter situation one vertical sync pulse (i.e. one frame) will be generated by including an integer number of the horizontal scanning lines (i.e. HPST). In this case, the pulse width is also counted by HPST. The rest is more or less equal to the horizontal pulse generator. The frequency of the free running pulse is: f H(free) f V(free) = ----------------2 x Vfp The pulse width of the free running mode is: tW(V) = TH(free) x [(VOPW<3:0>) + 2] x 2 1997 Dec 12 62
This function captures the 6 parameters, Hper, Hpol, Hpres, Vper, Vpol and Vpres such that the current value of these parameters is available for the microcontroller core (software) at all times. The mode change interrupt will be activated if: * The horizontal period changes * The vertical period changes * The horizontal polarity changes * The vertical polarity changes. 19.2.10 CONTROL All necessary control signals for the complete hardware mode detection are mentioned in Section 19.1.
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
19.2.11 THE DISPLAY PATTERN GENERATION For certain events such as disconnection with the host or the life test of monitor sets, it is convenient to have certain display patterns shown on the monitor as the indication of the operation of the monitor. The P83C880 provides two simple patterns, the white pattern and the cross hatch pattern for this purpose in the free running mode. In the free running mode, the intervals of HSYNC and VSYNC are determined by the 10-bit registers, HFP and VFP. Based on the HFP and VFP, the internal down counter will determine the starting or ending of the HSYNC and VSYNC. The starting position, ending position and the duration of the adjacent hatch lines are all related to the programmed value of HFP and VFP. As a matter of fact, the starting and ending position of the white pattern are
P83Cx80; P87C380
decided by the fixed number of FOSH clock and FOSV clock (see Fig.31). Therefore, the position or dimension of the white pattern is much related to HFP and VFP. The duration of every two hatch lines (accordingly, the number of hatch lines in the horizontal or vertical direction) will depend on two fixed numbers (32, 32) which divide HFP and VFP. For both white and cross hatch patterns, the displayed pattern might look different in the different timing modes and the symmetric display is not guaranteed. However, they should be sufficient to be used as the indicator to report the status of the monitor. Figure 31 demonstrates the display of the two patterns. Two flags: PATENA (SFR PWME2) and PATTYP (SFR PULCNT), are used to control the pattern display; for detailed usage of those control bits refer to Section 7.3.6 and Section 19.1.9.
handbook, full pagewidth
32 FOSH
16 FOSH
32 FOSH
32 FOSH
16 FOSH
32 HPST 32 HPST
16 HPST 1. THE WHITE PATTERN 2. THE CROSS HATCH
MGG040
Fig.31 Two self test display patterns.
19.2.12 CLAMP OUTPUT To facilitate the video processing in the following stage, the clamping pulse can be delivered on pin PWM8/CLAMP/P3.0 by setting flag CLMPEN (PULCNT.7) to HIGH. The clamping pulse always accompanies the HSYNCout pulse. Therefore, even in the free running mode the clamping pulse is still present as long as the CLMPEN bit is set. Flag FBPO (PULCNT.1) can be used to choose the front porch clamp pulse (FBPO = 0) or the back porch clamp pulse (FBPO = 1). The pulse width of the clamping output signal is fixed to 8 FOSH clocks.
The bit PHSI (PULCNT.0) is used to set the output polarity of HSYNCout and the clamping pulse. If PHSI is LOW then the output polarity will be positive, otherwise the output polarity is negative.
1997 Dec 12
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Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
19.3 System operation
P83Cx80; P87C380
After a successful power-on reset, the P83C880 will automatically start the mode detection and sync separation by default. The output pulses of HSYNC and VSYNC are delivered in the free running format by the default setting. Since it takes at least 5 frames to finalize the calculation of the HSYNC period, Hper, VSYNC period and Vper, it is better to wait until the stable state is reached to get the complete information after power-on reset. Accordingly, Hpol, Vpol, Hpres, Vpres and sync separation will be decided upon after Hper and Vper are settled. To prevent interfering the CPU too often, the interrupt request flag IE0 (SFR TCON) is only set if the mode (including frequency or polarity) is changed. IE0 will be cleared either by the CPU when the service routine is called (IT0 = 1) or by the service routine itself (IT0 = 0). If it is required to reduce power dissipation or if it is preferred to stabilize the entire system after power-on reset before mode detection is proceeded, the bit MARCH (SFR MDCST) can be cleared to logic 0. Mode detection can be activated at the desired moment later on by setting MARCH to a logic 1.
In fact, the detection of the Device Power Management Signalling (DPMS) modes like `Normal', `Standby', `Suspend', `Power off', etc. and sync separation are mixed together with the display mode detection. The mode detection function provides the hardware vehicle to facilitate the mode detection and related activities. Nevertheless, to use this facility to a maximum, the proper interaction between software and hardware is still essential. When VSYNC is absent and HSYNC is present, the polarity of HSYNC is always fixed. A software flow chart example is illustrated in Fig.32. 19.3.1 DISPLAY POWER MANAGEMENT SIGNALLING (DPMS) SPECIFICATION
According to the DPMS specification: Hfreq <10 kHz and Vfreq <10 Hz indicates that HSYNC and VSYNC are inactive. However, in the real application, there are no modes running with 10 kHz Hfreq15 kHz and 10 Hz Vfreq40 Hz. Therefore, Hfreq = 15 kHz and Vfreq = 40 Hz are chosen as the threshold to indicate an active or inactive signal for HSYNC and VSYNC respectively.
1997 Dec 12
64
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
handbook, full pagewidth
INTERRUPT OCCURS IE0 IS SET
YES
IS Hpres = 1?
NO
IS Vpres = 1?
NO
IS Vpres = 1?
YES
NO YES
IS VSEL = 1?
NO
IF CSYNC IN? (CHECK HSEL)
NO
YES
YES
CHANGE VSEL = 0
SET HSEL = 0 SET VSEL = 0
CHANGE VSEL = 1
SET HSEL = 1 SET VSEL = 1
MGG041
RETURN
Fig.32 Software procedure in system operation: Mode detection flow chart.
1997 Dec 12
65
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
20 POWER MANAGEMENT The P83C880 supports power management. The hardware mode detection complies to the Device Power Management Signalling (DPMS) according to the specification of VESA. The microcontroller is able to distinguish between `Normal', `Standby', `Suspend' and `Power off' mode by detecting the frequency of HSYNC and VSYNC. HSYNC is an active signal if its frequency is above 15 kHz; otherwise, it is inactive. For VSYNC 40 Hz is the threshold to judge if it is active or inactive. See also Section 19.3.1. The exact values for the threshold depend on the chosen crystal oscillator frequency: 10, 12 or 16 MHz. The information about the status of HSYNC and VSYNC can be represented by the bits, Hpres and Vpres in SFR MDCST (address F8H). Table 66 Display Power Management modes OPERATING MODES Normal Standby Suspend Power off 21 CONTROL MODES The microcontroller can operate in different control modes (e.g. for emulation or OTP programming) by means of a 10-bit serial code that is shifted into the RESET input. The signal at the XTAL1 pin serves as the shift clock. The code is built up as follows: 0 XXXXX 0101; whereby the first `0' is the start bit, followed by a 5-bit code and completed by `0101'. The 5-bit code determines the mode. Normal mode is reached when no code is shifted in, but the RESET pin remains HIGH for at least 10 cycles of the XTAL1 input plus 20 s. When an OTP Programming/Verification, Emulation or a Test mode should be entered, the timing must be as shown in Fig.34. The RESET signal is sampled on the rising edge of XTAL1. Set-up and hold times for the RESET signal with respect to the XTAL1 rising edge are 10 ns each. HSYNC active inactive active inactive Hpres 1 0 1 0
P83Cx80; P87C380
The combination of Hpres and Vpres in relation to the operating mode is shown in Table 66. In the case of DDC2AB protocol, apart from hardware mode detection, the protocol of ACCESS.bus also supports Device Power Management Signalling (DPMS) commands. In some operating modes the microcontroller might enter a kind of power saving mode, i.e. Idle or Power-down mode. In this situation the extremely low retention voltage of 1.8 V for internal memory can support the microcontroller to save its state before switching to Idle or Power-down mode. One set of I/O ports with the capability to drive LEDs can help to highlight the current operating mode of monitors. It is also possible to control the power consumption sources like heater, main supply etc., through an I/O port in a related operating mode.
VSYNC active active inactive inactive
Vpres 1 1 0 0
The procedure to enter a specific control mode is as follows: 1. Reset the microcontroller (CPU) by keeping the RESET signal HIGH for at least 10 XTAL1 clock cycles to escape any other control mode, plus at least 20 s (minimum of 24 internal clock cycles) to reset the internal logic. 2. Shift in the specific code for the required control mode (e.g. 0 11000 0101 for Emulation mode) via the RESET pin and the XTAL1 clock (MSB first). 3. After the 10th bit the RESET signal should go LOW within 9 cycles of XTAL1, otherwise the microcontroller will enter Normal mode. For the OTP Programming/Verification control modes see Chapter 22.
1997 Dec 12
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Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
22 ONE TIME PROGRAMMABLE (OTP) VERSION The OTP version P87C380 contains: * 32 kbytes ROM * 512 bytes RAM. Next to the 32 kbytes ROM, another extra 384 bytes are available. These bytes can be used for identification purposes or to indicate the version number, etc. These bytes are addressed via address lines A0 to A4. Access to the OTP for program execution is done in Normal mode. For writing and reading (Verification) of the program memory and of the extra 384 bytes, different control modes are used as shown in Table 67. Table 68 Pin assignments during Programming/Verification mode PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 VSS VSS A13 A12 A11 A10 A9 A8 XTAL1 (note 1) XTAL2 (note 1) VDD VSS WE DI5/DO5 DI6/DO6 OE DI4/DO4 A7 A6 A5 A4 A3 Note CONNECT TO PIN 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
P83Cx80; P87C380
The signals and waveforms are given in Table 69 and Fig.33. Pin connections to be used during Programming and Verification are given in Table 68. Table 67 Code for Programming/Verification of the OTP version P87C180A MEMORY ROM: 32 kbytes (program memory) Extra 384 bytes (memory) ROM: 32 kbytes (verification) CODE 010000 0101 010001 0101 011111 0101
CONNECT TO A2 A1 A0 RESET VSS VSS VSS VSS VSS VDD VSS A14 VPP DI3/DO3 DI2/DO2 DI1/DO1 DI0/DO0 DI7/DO7 VSS VSS
1. For driving the oscillator pins see Fig.10c.
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
Table 69 Timing table for programming; see Fig.33 SYMBOL tsu(AW) th(AW) tsu(AR) th(AR) tsu(D) th(D) tsu(prog) th(prog) tW(prog) tW(R) tACC(OE) tDZ(OE) PARAMETER address set-up time write address hold time write address set-up time read address hold time read data set-up time data hold time programming voltage set-up time programming voltage hold time programming pulse width read pulse width output enable access verify data float after OE 2 10 10 200 2 20 10 10 90 300 92 10 MIN. - - - - - - - - - - 122 - TYP.
P83Cx80; P87C380
MAX. - - - - - - - - - - 183 - s s ns ns s s s s s ns ns ns
UNIT
handbook, full pagewidth
10 s 10 s VIH VIL tsu(AW) th(AW)
WE
address VIH A0 to A13 V IL data in VIH DI0 to DI7 V IL data out VIH DO0 to DO7 V IL VPP VIL VIH VIL
ADDRESS VALID tsu(AR) DATA IN VALID tsu(D) th(D) DATA OUT VALID tsu(prog) th(prog) th(AR)
High Z
tDZ(OE)
VPP
tACC(OE) tW(R)
OE
MGG051
Fig.33 Programming waveforms.
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Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
handbook, full pagewidth
0
x x x x x 010
1
RESET
93 XTAL1 XTAL1
CODE
5 XTAL1
4 XTAL1 4 XTAL1
8 XTAL1
4 XTAL1
MBK517
Fig.34 Timing for OTP Programming/Verification.
23 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI Isource(max) Isink(max) Ptot Tstg Tamb 24 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices" ). supply voltage input voltage (all inputs) total maximum source current for all port lines total maximum sink current for all port lines total power dissipation storage temperature operating ambient temperature (for all devices) PARAMETER MIN. 4.4 -0.5 0.50 155 88.4 -60 -25 MAX. 5.5 0.67 165 170 +150 +85 UNIT V mA mA mW C C
VDD + 0.5 V
1997 Dec 12
69
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
25 DC CHARACTERISTICS VDD = 4.5 to 5.5 V; VSS = 0 V; Tamb = -25 to +85 C; all voltages with respect to VSS unless otherwise specified. SYMBOL Supply VDD IDD VPOR VDD(P) VPP IDD(P) IPP RESET RI(RESET) ILI VIL VIH input resistance RESET input leakage current LOW-level input voltage HIGH-level input voltage VDD = 4.5 V to 5.5 V VSS < VI < VDD VSS - 0.5 0.7VDD - - 20 60 180 10 0.3VDD VDD + 0.5 -10 VSS - 0.5 2.0 - - 0.8 VDD + 0.5 -10 VSS - 0.5 2.0 VO 0.4 V VO 1.0 V IOH HIGH-level pull-up output source current strong pull-up during 2 clock cycles weak pull-up Port 0 VIL VIH ILI IIT IOL LOW-level input voltage HIGH-level input voltage input leakage current input transition current LOW-level output sink current VI = 0.4VDD; VDD = 5 V VI = 0.5VDD; VDD = 5 V VO 0.4 V VO 1.0 V VSS - 0.5 0.7VDD -10 - 1.6 10 - - - - - - 0.3VDD VDD + 0.5 -100 -1000 - - V V A A mA mA VO = VDD - 0.4 V VO = VDD - 0.4 V 1.6 25 - - - - mA A 1.6 10 - - - - 0.8 VDD + 0.5 - - k A V V A V V A V V mA mA operating supply voltage operating supply current Power-on-reset voltage level fclk = 12 MHz fclk = 16 MHz PROGRAMMING SUPPLY supply voltage programming mode programming voltage supply current programming mode programming current 4.4 12.0 10.6 77.8 5.0 19.1 80.1 5.5 24.0 81.3 V V mA mA 12.75 13.0 4.4 20.1 25.2 3.6 5 29.4 36.1 3.9 5.5 30.9 38.4 4.2 V mA mA V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
HSYNCin/PROG and VSYNCin/OE IIL VIL VIH Input leakage current LOW-level input voltage HIGH-level input voltage VSS < VI < VDD
CSYNCin/P1.6 ILI VIL VIH IOL input leakage current LOW-level input voltage HIGH-level input voltage LOW-level output sink current VSS < VI < VDD
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
SYMBOL IOH PARAMETER HIGH-level pull-up output source current strong pull-up during 2 clock cycles weak pull-up VO = VDD - 0.4 V VO = VDD - 0.4 V 1.6 25 VSS - 0.5 0.7VDD VI = 0.4VDD; VDD = 5 V VI = 0.5VDD; VDD = 5 V VO = 0.4 V; VDD = 5V -10 - 3.0 CONDITIONS MIN.
P83Cx80; P87C380
TYP.
MAX.
UNIT
- - - - - - -
- -
mA A
Port 1: SCL/P1.0, SDA/P1.1, SCL1/P1.2 and SDA1/P1.3 VIL VIH ILI IIT IOL IOH LOW-level input voltage HIGH-level input voltage input leakage current input transition current LOW-level output sink current HIGH-level pull-up output source current strong pull-up during 2 clock cycles weak pull-up VO = VDD - 0.4 V VO = VDD - 0.4 V 1.6 25 VSS - 0.5 0.7VDD VI = 0.4VDD; VDD = 5 V VI = 0.5VDD; VDD = 5 V VO 0.4 V -10 - 1.6 - - - - - - - - - mA A 0.3VDD VDD + 0.5 -100 -1000 - V V A A mA
Port 1 and 3: VSYNCout/P1.4, HSYNCout/P1.5, PWM10/P1.7 and ADC0/P3.2 to ADC1/P3.3 VIL VIH ILI IIT IOL IOH LOW-level input voltage HIGH-level input voltage input leakage current input transition current LOW-level output sink current HIGH-level pull-up output source current strong pull-up during 2 clock cycles weak pull-up VO = VDD - 0.4 V VO = VDD - 0.4 V 1.6 25 VSS - 0.5 0.7VDD VI = 0.4VDD; VDD = 5 V VI = 0.5VDD; VDD = 5 V VO 0.4 V -10 - 1.6 - - - - - - - - - mA A 0.3VDD VDD + 0.5 -100 -1000 - V V A A mA
Port 2 and 3: P2.0/PWM0 to P2.7/PWM7 and Port P3.0/PWM8/CLAMP to P3.1/PWM9/PATOUT VIL VIH ILI IIT IOL IOH LOW-level input voltage HIGH-level input voltage input leakage current input transition current LOW-level output sink current HIGH-level pull-up output source current strong pull-up during 2 clock cycles weak pull-up VO = VDD - 0.4 V VO = VDD - 0.4 V 1.6 25 - - - - mA A 0.3VDD VDD + 0.5 -100 -1000 - V V A A mA
1997 Dec 12
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Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
SYMBOL INT1/VPP VIL VIH Note LOW-level input voltage HIGH-level input voltage IIH = 2 mA VSS - 0.5 - PARAMETER CONDITIONS MIN.
P83Cx80; P87C380
TYP. - -
MAX.
UNIT
0.2VDD - 0.1 V 12.6 8 V V
0.2VDD + 0.9 -
VIH - VDD input voltage with respect to VDD
1. This maximum applies at all times, including during power switching, and must be accounted for in power supply design. During a power-on process, the +12 V source used for external pull-up resistors should not precede the VDD of the P83C880, P83C180, P83C280 and P83C380 up their respective voltage ramps by more than this margin, nor, during a power-down process, should VDD precede +12 V down their respective voltage ramps by more than this margin. 26 DIGITAL-TO-ANALOG CONVERTER CHARACTERISTICS VDD = 5 V; VDDA = 5 V; Tamb = 27 C. SYMBOL VDD RESDAC Io(DAC) Io(DAC)(id) Vo(DAC) PARAMETER supply voltage DAC resolution operating current for each DAC channel DAC idle current DAC output level voltage output pin connected to VDDA via 40 k all 4 DAC channels shut-down output pin open at FFH code input; IOH = -1mA (note 1) at 00H code input; IOL = 1mA DLe tst Vo(T) Vo Note 1. The `negative' value denotes that the current is sourcing out from the chip into the load device through the output pin. differential non-linearity settling time output voltage variation due to temperature drift output voltage ripple Ttest > 20 ms output level 0.2 to 4.8 V TEST CONDITION - - - 0 MIN. 4.4 - 8 - - - TYP. - 2.5 61 VDDA - 0.2 +1 20 1.5 2 MAX. 5.5 UNIT V bit mA A V V V LSB ms mV/C mV
VDDA - 0.2 - - -1 - - - - - - - -
1997 Dec 12
72
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
27 AC CHARACTERISTICS VDD = 4.5 V to 5.5 V; VSS = 0 V; Tamb = -25 to + 85 C; all voltages with respect to VSS unless otherwise specified. SYMBOL fclk fPXE CXTAL1 PARAMETER crystal oscillator frequency PXE resonator frequency external capacitance at XTAL1 with crystal resonator with PXE resonator CXTAL2 external capacitance at XTAL2 with crystal resonator with PXE resonator Analog-to-Digital Converter (software) Vin(A) VAE tconv(ADC) comparator analog input voltages ADC0; ADC1 conversion error range conversion time (from any change in ADC input i.e. voltage level) VSS - - - - - VDD 12 7 V LSB s - - 20 20 27 27 pF pF - - 20 20 27 27 pF pF CONDITIONS VDD = 5 V VDD = 5 V MIN. 10 10 TYP. 12 12 MAX. 16 16 UNIT MHz MHz
DDC1 Mode(1) (transmit-only, unidirectional); see Figs 25 and 35 tDOV tVCLKH tVCLKL tt(mode) tsup(input) tsu(DDC1) Hfreq tW(HSYNC) HDCYC tir(HSYNC) tif(HSYNC) Vfreq tW(VSYNC) VDCYC tir(VSYNC) tif(VSYNC) output valid from VCLK VCLK high time VCLK low time mode transition time input filter spike suppression; for SDA, SCL and VSYNC DDC1 mode set-up time - 20 20 - - - - - - - - 5 - - - - - - - - - - 30 - - 800 200 - s s s ns ns s
Horizontal sync input for the mode detection; see Fig.36 HSYNC input frequency HSYNC input pulse width HSYNC input duty cycle HSYNC input rise time HSYNC input fall time notes 2 and 3 notes 2 and 3 15 0.25 - - - 150 8 25 100 100 kHz s % ns ns
Vertical Sync Input for the Mode Detection; see Fig.37 VSYNC input frequency VSYNC input pulse width VSYNC input duty cycle VSYNC input rise time VSYNC input fall time note 4 note 4 40 1 - - - 200 24 25 100 100 Hz note 5 % ns ns
1997 Dec 12
73
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
SYMBOL PARAMETER CONDITIONS
P83Cx80; P87C380
MIN. - - -
TYP.
MAX. - - 30
UNIT
Composite Sync Input for the Mode Detection; see Figs 38 and 39 TEQ(CSYNC) tWEQ(CSYNC) NEQ equalizing pulse period for CSYNC input equalizing pulse width for CSYNC input equalizing pulses plus the VSYNC interval 0.5 0.5 - note 5 note 6 note 5
Horizontal and Vertical Pulse Generation; see Figs 40 and 41 TH(free) tWH(free) tor(HSYNC) tof(HSYNC) td(in-out)(HSYNC) tdmax(HSYNCm) tW(HSYNCsub) tW(CLAMP) TV(free) tWV(free) tor(VSYNC) tof(VSYNC) td(in-out)(VSYNC) tdmax(VSYNCm) tW(VSYNCsub) ttLH(sce) ttHL(sce) tPLH(scd) tPHL(scd) Notes 1. For the DDC2 Mode (bidirectional I2C-bus mode), refer to the standard I2C-bus specification. 2. The actual sync width has to fulfil both requirements, maximum pulse width tW(HSYNC) = 8.0 s and maximum duty cycle HDCYC of 25%, at the same time. 3. The polarity of the horizontal sync pulse is said to be positive if the HIGH period is shorter than the LOW period. 4. The actual sync width has to fulfil both requirements, maximum pulse width tW(VSYNC) = 24 horizontal line periods and maximum duty cycle VDCYC of 25%, at the same time. 1997 Dec 12 74 horizontal pulse period in free running horizontal pulse width in free running HSYNC output pulse rise time HSYNC output pulse fall time HSYNC output delay to input HSYNC output maximum delay after missing HSYNC HSYNC output substitution pulse width CLAMP pulse width vertical pulse period in free running vertical pulse width in free running VSYNC output pulse rise time VSYNC output pulse fall time VSYNC output delay to input VSYNC output maximum delay after missing VSYNC VSYNC output substitution pulse width 10 0.4 30 24 - - - 0 0.4 - - 22 24 - - - - - 31 26 - - - - - - - 24 27 - - - - - - - 66 2.5 32 28 100 350 2.5 125 2.5 2048 32 26 30 250 1 16 s s ns ns ns ns s ns s note 5 note 5 ns ns ns note 5 note 5
td(HSYNC-CLAMP) CLAMP pulse delay to HSYNC input
Slope control port LOW-to-HIGH transition delay while slope control enabled HIGH-to-LOW transition delay while slope control enabled 0.1VDD to 0.9VDD; note 7 0.9VDD to 0.1VDD; note 7 25 25 - - 100 100 10 10 ns ns ns ns
LOW-to-HIGH propagation delay while 0.1VDD to 0.9VDD; slope control disabled load = 50 pF HIGH-to-LOW propagation delay while 0.9VDD to 0.1VDD; slope control disabled load = 50 pF
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
5. Unit is HSYNC line period: Tline(HSYNC). 6. Unit is HSYNC pulse width: tW(HSYNC). 7. This transition delay has to be loaded independent for capacitances up to 50 pF.
P83Cx80; P87C380
handbook, full pagewidth
transmit only mode (DDC1)
bidirectional mode (DDC2)
SCL tt(mode) SDA
VCLK
MGG052
Fig.35 Mode transition from DDC1 to DDC2.
handbook, full pagewidth
HSYNC
tif(HSYNC)
tW(HSYNC) HDCYC
tir(HSYNC) THSYNC
MGG053
Fig.36 Horizontal sync input signal.
handbook, full pagewidth
VSYNC
tif(VSYNC)
tW(VSYNC) VDCYC
tir(VSYNC) TVSYNC
MGG054
Fig.37 Vertical sync input signal.
1997 Dec 12
75
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
handbook, full pagewidth tW(CSYNC)
TEQ(CSYNC)
1/Hfreq
CSYNC tWEQ(CSYNC) HSYNC
VSYNC 2nd field 1st field
NEQ CSYNC
HSYNC
VSYNC 2nd field 1st field
MGG055
Fig.38 Standard composite sync pulse wave forms.
1997 Dec 12
76
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
handbook, full pagewidth
HSYNC tW(HSYNC) 1/Hfreq
VSYNC tW(VSYNC)
CSYNC-1
CSYNC-2 tWEQ(CSYNC) TEQ(CSYNC) CSYNC-3
CSYNC-4
CSYNC-5
CSYNC-6 NEQ
MGG056
Fig.39 Composite sync pulse wave forms.
1997 Dec 12
77
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
handbook, full pagewidth
HSYNC
HSYNCout (free running)
tof(HSYNC)
tWH(free)
tor(HSYNC) TH(free)
HSYNCout (sync/ substitution) td(in-out)(HSYNC) HSYNCout (sync/substitution with fixed pulse width) tW(HSYNCsub) CLAMP (clamp pulse at back porch) td(HSYNC-CLAMP) CLAMP (clamp pulse at front porch) tdmax(HSYNCm) tW(HSYNCsub) tdmax(HSYNCm) tW(HSYNCsub)
tW(CLAMP)
td(HSYNC-CLAMP)
MGG057
tW(CLAMP)
Fig.40 Horizontal sync output pulse.
1997 Dec 12
78
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
P83Cx80; P87C380
handbook, full pagewidth
VSYNC
VSYNCout (free running)
tof(VSYNC)
tWV(free)
tor(VSYNC) TV(free)
VSYNCout (sync/ substitution) tdmax(VSYNCm)
td(in-out)(VSYNC)
tW(VSYNCsub)
MGG058
Fig.41 Vertical sync output pulse.
1997 Dec 12
79
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
28 PACKAGE OUTLINE SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)
P83Cx80; P87C380
SOT270-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 wM (e 1) MH b 42 22
pin 1 index E
1
21
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 38.9 38.4 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.9 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT270-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-02-13 95-02-04
1997 Dec 12
80
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
29 SOLDERING 29.1 Introduction
P83Cx80; P87C380
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 29.2 Soldering by dipping or by wave
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 29.3 Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.
1997 Dec 12
81
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
30 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
P83Cx80; P87C380
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 31 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 32 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Dec 12
82
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.
NOTES
P83Cx80; P87C380
1997 Dec 12
83
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
457041/1200/01/pp84
Date of release: 1997 Dec 12
Document order number:
9397 750 03171

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